Erase operation in 3D NAND flash memory including pathway impedance compensation

An apparatus comprising:

• a first conductive line;
• a second conductive line;
• a first select line;
• a second select line;
• a NAND string of memory cells comprising a first select transistor having a first terminal connected to the first conductive line and a second terminal connected to the first select line, a second select transistor having a third terminal connected to the second conductive line and a fourth terminal connected to the second select line, and non-volatile memory cells connected between the first select transistor and the second select transistor, the non-volatile memory cells comprising a NAND string channel;
• and
• a control circuit in communication with the first conductive line, the second conductive line, the first select line, and the second select line, the control circuit configured to:
• apply a first gate induced drain leakage (GIDL) voltage pulse to cause a first GIDL current to flow from the first select transistor to the NAND string channel during a first transient period and a steady state period of the first GIDL voltage pulse;
• apply a second GIDL voltage pulse to cause a second GIDL current to flow from the second select transistor to the NAND string channel during a first transient period and a steady state period of the second GIDL voltage pulse and while the first GIDL current flows from the first select transistor to the NAND string channel, wherein the first GIDL current and the second GIDL current have substantially the same magnitude during the first transient periods and the steady state periods of the first GIDL voltage pulse and the second GIDL voltage pulse, wherein the first GIDL voltage pulse and the second GIDL voltage pulse have different steady state magnitudes;
• and
• apply an erase enable voltage to control gates of the memory cells on the NAND string to perform a two-sided GIDL erase based on the first GIDL current and the second GIDL current.

A method comprising:

• causing a first gate-induced drain leakage (GIDL) voltage pulse between a first terminal and a second terminal of a first select transistor of a NAND string, including applying a first voltage pulse having a first start time to a first end of a first conductive pathway that has a second end connected to the first select transistor, the first voltage pulse having a second start time at the second end of the first conductive pathway;
• causing a second GIDL voltage pulse between a third terminal and a fourth terminal of a second select transistor of the NAND string, including applying a second voltage pulse having a third start time to a first end of a second conductive pathway that has a second end connected to the second select transistor, the second voltage pulse has a fourth start time at the second end of the second conductive pathway, the first start time and the third start time are different, the second start time and fourth start time are substantially the same, the first conductive pathway and the second conductive pathway having different impedances;
• and
• applying an erase enable voltage to control gates of non-volatile memory cells of the NAND string while the first GIDL voltage pulse is at a first steady state magnitude and the second GIDL voltage pulse is at second steady state magnitudes.

An apparatus comprising:

• a first pathway having a first end and a second end;
• a second pathway having a first end and a second end;
• a NAND string comprising a first select transistor connected to the second end of the first pathway, a second select transistor connected to the second end of the second pathway, and non-volatile memory cells connected between the first select transistor and the second select transistor;
• an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of the non-volatile memory cells, the erase controller configured to:
• apply a first voltage pulse having a first ramp time to the first end of the first pathway;
• and
• apply a second voltage pulse having a second ramp time to the first end of the second pathway, the first ramp time is different than the second ramp time, wherein the difference between the first ramp time and the second ramp time is configured to compensate for different impedances within the first pathway and the second pathway such that a first erase voltage pulse at the first select transistor is substantially symmetric with a second erase voltage pulse at the second select transistor.

An apparatus comprising:

• a NAND string comprising a first select transistor having a first terminal and a second terminal, a second select transistor having a first terminal and a second terminal, and non-volatile memory cells connected between the first select transistor and the second select transistor;
• a first pathway having a first end and a second end connected to the first terminal of the first select transistor;
• a second pathway having a first end and a second end connected to the first terminal of the second select transistor;
• a third pathway having a first end and a second end connected to the second terminal of the first select transistor;
• a fourth pathway having a first end and a second end connected to the second terminal of the second select transistor;
• and
• an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of the non-volatile memory cells, the erase controller configured to:
• apply a first voltage pulse to both the first end of the third pathway and to the first end of the fourth pathway;
• start to apply a second voltage pulse to the first end of the first pathway in response to the first voltage pulse applied to both the first end of the third pathway and to the first end of the fourth pathway reaching a first voltage magnitude, the second voltage pulse having a first value for a voltage pulse attribute;
• and
• start to apply a third voltage pulse to the first end of the second pathway in response to the first voltage pulse applied to both the first end of the third pathway and to the first end of the fourth pathway reaching a second voltage magnitude, the third voltage pulse having a second value for the voltage pulse attribute, wherein the first value and the second value are configured to compensate for different impedances within the first pathway and the second pathway such that a first erase voltage pulse at the first select transistor is substantially symmetric with a second erase voltage pulse at the second select transistor.