Memory devices with distributed block select for a vertical string driver tile architecture

A memory device, comprising:

• a number of pairs of tiles, each pair of tiles of the number of pairs of tiles including a first tile and a second tile, each of the first tile and the second tile including:
• a portion of a distributed block select circuit for the number of pairs of tiles;
• additional circuity;
• and
• a page buffer having an area greater than a combined area of the portion of the distributed block select circuit and the additional circuitry of the associated tile.

A memory device, comprising:

• a first tile pair including a first tile, a second tile, and a first vertical string driver offset from the first tile and the second tile in a first direction, the first tile including a first portion of a distributed block select circuitry and the second tile including a second portion of the distributed block select circuitry;
• and
• a second tile pair including a third tile, a fourth tile, and a second vertical string driver offset from the third tile and the fourth tile in the first direction, the third tile including a third portion of the distributed block select circuitry and the fourth tile including a fourth portion of the distributed block select circuitry;
• wherein each of the first portion of the distributed block select circuity, the second portion of the distributed block select circuity, the third portion of the distributed block select circuity, and the fourth portion of the distributed block select circuity are offset from every other portion of the distributed block select circuitry in a second, different direction.