Ternary memory cell and ternary memory cell arrangement

A ternary memory cell comprising:

• a first match line node, a second match line node, a first lookup node, and a second lookup node;
• a first remanent-polarizable memory cell comprising a first terminal, a second terminal, and a control terminal to control an electrical behavior of the first terminal and the second terminal of the first remanent-polarizable memory cell;
• and
• a second remanent-polarizable memory cell comprising a first terminal, a second terminal, and a control terminal to control an electrical behavior of the first terminal and the second terminal of the second remanent-polarizable memory cell,
• wherein the first terminal of the first remanent-polarizable memory cell is electrically connected to the first match line node, wherein the second terminal of the second remanent-polarizable memory cell is electrically connected to the second match line node, and wherein the second terminal of the first remanent-polarizable memory cell and the first terminal of the second remanent-polarizable memory cell are electrically connected with one another, and
• wherein the control terminal of the first remanent-polarizable memory cell is electrically connected to the first lookup node and wherein the control terminal of the second remanent-polarizable memory cell is electrically connected to the second lookup node.

A ternary memory cell arrangement comprising:

• a plurality of ternary memory cells;
• a lookup circuit coupled to a plurality of lookup line drivers and configured to send a lookup word to a plurality of first subsets of the plurality of ternary memory cells, each first subset of the plurality of first subsets defines a corresponding stored word;
• and
• an address encoder coupled to a plurality of match line drivers and configured to output an address signal associated with a match or mismatch of the lookup word with the corresponding stored word of each of the plurality of first subsets,
• wherein each ternary memory cell of the plurality of ternary memory cells is switchable into a first matching state, a second matching state, and a third matching state, wherein each ternary memory cell of the plurality of ternary memory cells comprises:
• a first ferroelectric memory cell and a second ferroelectric memory cell in a parallel arrangement or a serial arrangement, wherein each of the first ferroelectric memory cell and the second ferroelectric memory cell is switchable into a first ferroelectric memory cell state and a second ferroelectric memory cell state;
• and
• wherein the first matching state is defined by the first ferroelectric memory cell in the first ferroelectric memory cell state and the second ferroelectric memory cell in the second ferroelectric memory cell state, wherein the second matching state is defined by the first ferroelectric memory cell in the second ferroelectric memory cell state and the second ferroelectric memory cell in the first ferroelectric memory cell state, and wherein the third matching state is defined by the first ferroelectric memory cell and the second ferroelectric memory cell being in the same ferroelectric memory cell state.