Energy efficient phase change random access memory cell array write via controller-side aggregation management

A memory system comprising:

• a memory controller;
• and
• a memory device including a memory cell array,
• the memory cell array including a plurality of bit lines and a plurality of blocks, each block including a plurality of word lines, each word line including a plurality of phase-change random access memory (PRAM) cells connected, respectively, to the plurality of bit lines,
• the memory controller being configured to buffer a first number of write requests each of which includes write data and configured to perform a write operation that includes a reset phase and a subsequent set phase,
• the memory controller being further configured such that,
• the reset phase includes controlling the memory device to selectively reset resistivity states of PRAM cells, from among the PRAM cells included in two or more first word lines of a selected block, to a high resistivity state in accordance with the write data included in the first number of write requests, and
• the set phase includes controlling the memory device to selectively set resistivity states of PRAM cells, from among the PRAM cells included in the two or more first word lines, to a low resistivity state in accordance with the write data included in the first number of write requests.