Tuning voltages in a read circuit
AssigneeMicron Technology, Inc.
InventorsGeorge B. Raad, John F. Schreck
Life of this patent
Estimating the term…
Abstract
Techniques are provided for tuning the voltages of a circuit for reading a memory cell capable of storing three or more logic states. To read the memory cell, a charge may be transferred between a digit line and a sense component using a charge transfer device. The gate of the charge transfer device may initially be biased to a first voltage and subsequently tuned to a second voltage to optimize the sense window. After biasing the gate of the charge transfer device to the second voltage, the memory cell may discharge its charge onto the digit line, which may result in the digit line being biased to a third voltage. Based on whether the third voltage exceeds the second voltage, the charge transfer device may transfer the charge associated with the memory cell.
Claims25
A method, comprising:
- biasing a gate of a first transistor to a first voltage, the first transistor coupled with a digit line and a sense component and configured to transfer a charge between the digit line and the sense component during a read operation;
- deactivating, after biasing the gate of the first transistor to the first voltage, a second transistor to isolate the gate of the first transistor from the sense component;
- biasing the gate of the first transistor to a second voltage after deactivating the second transistor;
- and
- determining a logic state of a memory cell at the sense component based at least in part on biasing the gate of the first transistor to the second voltage.
An apparatus, comprising:
- a memory cell coupled with a digit line;
- a sense component comprising a node;
- a first transistor coupled with the sense component and configured to transfer charge between the digit line and the node of the sense component during a read operation;
- a second transistor coupled with a gate of the first transistor and the sense component, the second transistor configured to apply a first voltage to the gate of the first transistor that compensates for a threshold voltage associated with the first transistor;
- and
- a capacitor coupled with the gate of the first transistor and configured to bias the gate of the first transistor to a second voltage different than the first voltage.
An apparatus, comprising:
- a memory cell coupled with a digit line;
- a sense component;
- a first transistor coupled with the digit line and the sense component;
- a second transistor coupled with a gate of the first transistor and the sense component;
- a controller coupled with the memory cell, the controller configured to;
- bias the gate of the first transistor to a first voltage;
- isolate the gate of the first transistor from the sense component by deactivating, after biasing the gate of the first transistor to the first voltage, the second transistor;
- bias the gate of the first transistor to a second voltage after isolating the gate of the first transistor from the sense component;
- and
- determine a logic state of the memory cell at the sense component based at least in part on biasing the gate of the first transistor to the second voltage.
Dependencies are inferred from the claim text.