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US 10,650,883 B2Granted
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorTakashi Yamaki
Life of this patent
Estimating the term…
Abstract
In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.
Claims13
A semiconductor device comprising:
- first through third memory modules used as a work area or a program area of a processor,
- a plurality of first memory cells included in the first memory module;
- a plurality of second memory cells included in the second memory module;
- a plurality of third memory cells included in the third memory module;
- a first control signal line coupled with the first memory module and the second memory module to transmit a control signal to the first and second memory modules for setting each of the first and second memory modules to the first state or the second state;
- a second control signal line coupled with the first memory module and the third memory module to transmit the control signal from the first memory module to the third memory module, without being coupled with the second memory module;
- and
- a first wiring disposed in the first memory module, and coupled with the first control signal line and the second control signal line for transmitting the control signal from the first control signal line to the second control signal line,
- wherein the first memory module includes a first peripheral circuit for reading data from the plurality of first memory cells and writing data to the plurality of first memory cells,
- wherein the first peripheral circuit includes a first sense amplifier (SA) for reading data from the plurality of first memory cells,
- wherein the second memory module includes a second peripheral circuit for reading data from the plurality of second memory cells and writing data to the plurality of second memory cells,
- wherein the second peripheral circuit includes a second sense amplifier (SA) for reading data from the plurality of second memory cells,
- wherein the third memory module includes a third peripheral circuit for reading data from the plurality of third memory cells and writing data to the plurality of third memory cells,
- wherein the third peripheral circuit includes a third sense amplifier (SA) for reading data from the plurality of third memory cells,
- wherein each of the first through third memory modules has a first state to consume less electric power than in a second state, and
- wherein the number of the plurality of first memory cells included in the first memory module is greater than the number of the plurality of second memory cells included in the second memory module.
13 more elements
A semiconductor device comprising:
- a CPU;
- a first memory module including a plurality of first memory cells;
- a second memory module including a plurality of second memory cells;
- a third memory module including a plurality of third memory cells;
- a first memory block including the first and second memory modules;
- a second memory block including the third memory module;
- a first control signal line coupled with the first memory module and the second memory module to transmit a control signal to the first and second memory modules for setting each of the first and second memory modules to the first state or the second state;
- a second control signal line coupled with the first memory module and the third memory module to transmit the control signal from the first memory module to the third memory module;
- and
- a first wiring disposed in the first memory module, and coupled with the first control signal line and the second control signal line for transmitting the control signal from the first control signal line to the second control signal line;
- wherein a plurality of memory modules including the first memory module and the second memory module, and located in the first memory block is coupled with the CPU without being coupled with any memory modules,
- wherein a plurality of memory modules including the third memory module, and located in the second memory block is coupled with the CPU through at least one of the plurality of memory modules located in the first memory block,
- wherein each of the first through third memory modules has a first state to consume less electric power than in a second state,
- wherein the number of the plurality of first memory cells is greater than the number of the plurality of second memory cells, and
- wherein the second control signal line is only coupled with the first memory module within a region of the first memory block.
12 more elements
Dependencies are inferred from the claim text.