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US 10,650,882 B2Granted
Static random access memory with a supplementary driver circuit and method of controlling the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin, Yen-Huei Chen
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Abstract
A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM.
Claims20
A static random access memory (SRAM) comprising:
- a first memory cell array;
- a second memory cell array;
- a first data line and a complementary data line to the first data line, each connected to the first memory cell array and the second memory cell array;
- a primary driver circuit connected to the first data line;
- a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to
- pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM based on at least a first AND output signal, receive a supplementary driver circuit enable signal, wherein the supplementary driver circuit enable signal is based on sensing a first signal of the first data line, and
- wherein the supplementary driver circuit enable signal is different from a second signal of the complementary data line to the first data line, the supplementary driver circuit comprises:
- a first AND gate comprising a first terminal, a second terminal and a third terminal, wherein
- the first terminal of the first AND gate is configured to receive the first signal and is coupled to the first data line,
- the second terminal of the first AND gate is configured to receive the supplementary driver circuit enable signal and is coupled to a first supplementary driver control line, and
- the third terminal of the first AND gate is configured to generate the first AND output signal.
8 more elements
A semiconductor device comprising:
- a static random access memory (SRAM) comprising:
- a first memory cell array;
- a second memory cell array;
- a first data line connected to the first memory cell array and the second memory cell array;
- a second data line connected to the first memory cell array and the second memory cell array;
- a primary driver circuit connected to the first data line and the second data line;
- and
- a supplementary driver circuit connected to the first data line and the second data line;
- wherein the supplementary driver circuit is configured to pull a voltage level of the first data line or the second data line to a first voltage level during a write operation of the SRAM based on at least an AND output signal, and receive
- a first signal of the first data line or a second signal of the second data line, and
- another signal, different from the first signal of the first data line and the second signal of the second data line, and based on sensing the first signal of the first data line,
- the supplementary driver circuit comprises an AND gate, wherein
- a first terminal of the AND gate is configured to receive the first signal or the second signal and is coupled to the first data line or the second data line,
- a second terminal of the AND gate is configured to receive the another signal and is coupled to a first control line, and
- a third terminal of the AND gate is configured to generate the AND output signal.
12 more elements
A method of controlling a static random access memory (SRAM), the method comprising:
- receiving a first signal on a first data line and a second signal on a second data line, wherein the first data line and the second data line are coupled to a memory cell;
- receiving a word line signal on a word line coupled to the memory cell;
- activating a supplementary driver circuit coupled to the first data line and the second data line, wherein the activating the supplementary driver circuit comprises receiving an enable signal on a first control line, and generating a first AND output signal by an output terminal of a first AND gate, a first input terminal of the first AND gate being coupled to the first data line, and a second input terminal of the first AND gate being coupled to the first control line, wherein the first control line is coupled to the supplementary driver circuit;
- and
- selectively adjusting a voltage signal of the first data line or the second data line in response to the enable signal.
2 more elements
Dependencies are inferred from the claim text.