Variable width memory module supporting enhanced error detection and correction
AssigneeRambus Inc.
InventorsFrederick A. Ware, John Eric Linstadt, Kenneth L. Wright
Life of this patent
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Abstract
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
Claims19
A data buffer component comprising:
- a primary data port to couple to a memory-controller component;
- first and second secondary data ports to couple to respective first and second memory components;
- and
- multiplexing circuitry supporting a first access mode and a time-division-multiplexing mode, wherein:
- in the first access mode, the multiplexing circuitry communicates, to the primary data port, first data bursts from the first secondary data port separate from second data bursts from the second secondary data port;
- and
- in the time-division-multiplexing mode, the multiplexing circuitry communicates, to the primary data port, ones of the first data bursts from the first secondary data port interleaved with ones of the second data bursts from the second secondary data port.
A method of communicating data between first and second memory components and a memory-controller component, the method comprising:
- in a first access mode, communicating first data bursts from the first memory component to the memory-controller component separate from second data bursts from the second memory component to the memory-controller component;
- and
- in a time-division-multiplexing mode, communicating ones of the first data bursts from the first memory component to the memory-controller component interleaved with ones of the second data bursts from the second memory component.
A data buffer component comprising:
- a primary data port to couple to a memory-controller component;
- first and second secondary data ports to couple to respective first and second memory components;
- and
- means for supporting a first access mode and a time-division-multiplexing mode, wherein:
- in the first access mode, communicating to the primary data port first data bursts from the first secondary data port separate from second data bursts from the second secondary data port;
- and
- in the time-division-multiplexing mode, communicating to the primary data port ones of the first data bursts from the first secondary data port interleaved with ones of the second data bursts from the second secondary data port.
Dependencies are inferred from the claim text.