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US 10,650,871 B2Granted
Read margin control circuit determining data valid window, memory controller including the same, and electronic device
AssigneeSamsung Electronics Co., Ltd.
InventorsKwanyeob Chae, Sanghune Park
Life of this patent
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Abstract
A read margin control circuit is provided. The read margin control circuit includes a delay circuit that delays a data input/output signal and generates delay signals having different phases from each other, a sampler that samples the delay signals based on a data strobe signal to generate sampling values, and a determiner configured to determine a data valid window of the data input/output signal based on the sampling values.
Claims20
A read margin control circuit comprising:
- a delay circuit configured to receive a data input/output signal and generate a plurality of delay signals by delaying the data input/output signal, the plurality of delay signals having different phases from each other;
- a sampler configured to sample the plurality of delay signals of the data input/output signal based on a data strobe signal to generate a plurality of sampling values;
- and
- a determiner configured to determine a data valid window of the data input/output signal based on the plurality of sampling values.
1 more element
A memory controller comprising:
- a delay circuit configured to receive a data input/output signal from a memory device to generate a first delay signal, a plurality of second delay signals which are less delayed than the first delay signal, and a plurality of third delay signals which are more delayed than the first delay signal, by delaying the data input/output signal;
- a sampler configured to sample the first delay signal, the plurality of second delay signals, and the plurality of third delay signals at a rising edge of a data strobe signal transmitted from the memory device and to sample the first delay signal, the plurality of second delay signals, and the plurality of third delay signals at a falling edge of the data strobe signal;
- and
- a determiner configured to determine a data valid window of the data input/output signal based on a first rising sampling value and a first falling sampling value of the first delay signal, which are respectively sampled at the rising edge and the falling edge.
1 more element
An electronic device comprising:
- a memory device configured to generate a data input/output signal and a data strobe signal synchronized with the data input/output signal;
- and
- a memory controller configured to generate a plurality of delay signals having different phases by delaying the data input/output signal, to generate a plurality of sampling values by sampling the plurality of delay signals of the data input/output signal based on the data strobe signal, and to determine a data valid window of the data input/output signal based on the plurality of sampling values.
Dependencies are inferred from the claim text.