Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory

A memory device comprising:

• a substrate;
• a characteristic adaption circuit formed in a front-end-of-the-line (FEOL) logic layer on the substrate;
• and
• a plurality of back-end-of-the-line (BEOL) memory layers formed above the logic layer,
• wherein the characteristic adaption circuit is configured to access a repository formed in the memory, the repository comprising delta values representing a degree to which an access signal applied to the one or more layers of the memory during an access operation is adjusted.

A method comprising:

• receiving, by a selector circuit, a memory address indicating a layer of one or more layers in a memory, the one or more layers formed above a logic layer, the logic layer comprising the selector circuit;
• selecting, by the selector circuit, a delta value from a repository formed in the memory, the repository comprising delta values representing a degree to which an access signal applied to the one or more layers of the memory during an access operation is adjusted;
• and
• adjusting the access signal applied to the one or more layers of the memory based on the delta value.