Shift register unit and driving method thereof, gate driving circuit and display panel

A shift register unit, comprising:

• an inputting circuit, coupled to a cascade inputting terminal for receiving an inputting signal and a first node, and configured to pull-up or pull-down a voltage at the first node under control of the inputting signal;
• a first outputting circuit, coupled to a clock signal terminal for providing a clock signal and a second node, and configured to output the clock signal as a first outputting signal at a gate voltage outputting terminal under control of the clock signal;
• a reset controlling circuit, coupled to a third node and a first level supplying terminal for providing a first level signal, and configured to control an operation of a first resetting circuit;
• the first resetting circuit, coupled to the second node, the gate voltage outputting terminal and the first level supplying terminal, and configured to reset a voltage at the second node and a voltage at the gate voltage outputting terminal under control of the reset controlling circuit;
• and
• a pulling-up circuit comprising at least two transistors, wherein each of the at least two transistors is coupled to a DC signal inputting terminal for providing a DC signal,
• wherein the at least two transistors are configured to be alternatively turned on under control of the DC signal, so as to pull up the voltage at the second node.