Array substrate and display panel

A display panel, comprising:

• an array substrate, wherein the array substrate comprises a display area and a non-display area surrounding the display area,
• wherein the display area comprises a first corner, and a plurality of data lines extending along a first direction and a plurality of gate lines extending along a second direction are provided in the display area, and the first direction intersects with the second direction;
• wherein the non-display area comprises:
• a first non-display area, a second non-display area and a first corner non-display area, the first corner non-display area is adjacent to the first non-display area and the second non-display area, the first non-display area extends along the first direction, and the second non-display area extends along the second direction;
• wherein the first corner non-display area is adjacent to the first corner, and at least one data end circuit, at least one first signal line section and at least one first shift register are disposed in the first corner non-display area, the at least one data end circuit is disposed at a side of the at least one first shift register close to the display area, and the at least one first signal line section corresponding to and connected to the at least one data end circuit is located at the side of the at least one first shift register close to the display area;
• wherein at least one second signal line section and at least one second shift register are provided in the first non-display area, and the second signal line section is located at a side of the at least one second shift register away from the display area;
• wherein the second signal line section is connected to the first signal line section through a first bridge line so as to provide a signal to the at least one data end circuit, and the first bridge line is located in a metal layer different from metal layers where the first signal line section and the second signal line section are located;
• and
• wherein each of the at least one first shift register is connected to at least one of the plurality of gate lines, and each of the at least one second shift register is connected to at least one of the plurality of gate lines.