Shift register unit, shift register, driving method, display panel and display apparatus

A driving method for a gate shift register unit comprising an activation signal terminal and a deactivation signal terminal;

• a reset signal terminal;
• a first level signal terminal and a second level signal terminal;
• a first control terminal;
• a first clock signal terminal and a second clock signal terminal;
• an output terminal;
• a first node and a second node;
• a first node control unit electrically connected to the first control terminal, the activation signal terminal, the first level signal terminal, the second level signal terminal, the deactivation signal terminal, the first node, and the second node, and configured to transfer a signal at the first level signal terminal or at the second level signal terminal to the first node under a control of potential signals at the activation signal terminal, the deactivation signal terminal, the first control terminal, and the second node;
• a second node control unit electrically connected to the second level signal terminal, the second clock signal terminal, the first node, and the second node, and configured to transfer a signal at the second level signal terminal or at the second clock signal terminal to the second node under a control of a potential signal at the first node;
• a reset unit electrically connected to the reset signal terminal, the second level signal terminal, the first node, and the output terminal, and configured to reset signals at the first node and the output terminal under a control of a potential signal at the reset signal terminal;
• and an output unit electrically connected to the first clock signal terminal, the second clock signal terminal, the second level signal terminal, the first node, the second node, and the output terminal, and configured to transfer a signal at the first level signal terminal, the second level signal terminal, or the second clock signal terminal to the output terminal under a control of the first clock signal terminal, the first node, and the second node, wherein:
• an operation timing sequence of the gate shift register unit includes a data writing phase and an image holding phase;
• at the data writing phase, a single pulse trigger signal is supplied to the activation signal terminal, a first clock signal is supplied to the first clock signal terminal, a second clock signal is supplied to the second clock signal terminal, a first level signal is supplied to the first level signal terminal, a second level signal is supplied to the second level signal terminal, a second level signal is supplied to the first control terminal, the output terminal of the gate shift register unit outputs a scanning driving signal, and a half first clock signal cycle delay exists between the first clock signal and the second clock signal;
• and
• at the image holding phase, a pulse signal is supplied to the first control terminal, another pulse signal is supplied sequentially to the first clock signal terminal and the second clock signal terminal, a first level signal is supplied to the first level signal terminal, a second level signal is supplied to the second level signal terminal, and the output terminal of the gate shift register unit outputs a single pulse signal.

A gate shift register, comprising a first stage to an N-th stage cascaded gate shift register units, wherein N is a positive integer greater than 1, and each gate shift register unit comprises:

• an activation signal terminal and a deactivation signal terminal;
• a reset signal terminal;
• a first level signal terminal and a second level signal terminal;
• a first control terminal;
• a first clock signal terminal and a second clock signal terminal;
• an output terminal;
• a first node and a second node;
• a first node control unit electrically connected to the first control terminal, the activation signal terminal, the first level signal terminal, the second level signal terminal, the deactivation signal terminal, the first node, and the second node, and configured to transfer a signal at the first level signal terminal or at the second level signal terminal to the first node under a control of potential signals at the activation signal terminal, the deactivation signal terminal, the first control terminal, and the second node, wherein
• the first node control unit includes a transistor, and
• the transistor is electrically connected to the first level signal terminal, the first control terminal, and the first node;
• a second node control unit electrically connected to the second level signal terminal, the second clock signal terminal, the first node, and the second node, and configured to transfer a signal at the second level signal terminal or at the second clock signal terminal to the second node under a control of a potential signal at the first node;
• a reset unit electrically connected to the reset signal terminal, the second level signal terminal, the first node, and the output terminal, and configured to reset signals at the first node and the output terminal under a control of a potential signal at the reset signal terminal;
• and
• an output unit electrically connected to the first clock signal terminal, the second clock signal terminal, the second level signal terminal, the first node, the second node, and the output terminal, and configured to transfer a signal at the first level signal terminal, the second level signal terminal, or the second clock signal terminal to the output terminal under a control of the first clock signal terminal, the first node, and the second node.