Electronic neuromorphic system, synaptic circuit with resistive switching memory and method of performing spike-timing dependent plasticity

An electronic neuromorphic system comprising a multi-layer structure wherein an intermediate layer (Lx) comprises a first set (N) of pre-synaptic neurons and a subsequent layer (LX+1) comprises a second set (M) of post-synaptic neurons, synaptic circuits performing spike-timing dependent plasticity (STDP) being interposed between the pre-synaptic neurons of the first set (N) and the post-synaptic neurons of the second set (M), each synaptic circuit comprising:

• a memristor having a variable resistance value (R) and being configured to receive a first signal (VTE) from the pre-synaptic neuron;
• transistor structure connected in series with the memristor and being configured for receiving a second signal (VCG) from the pre-synaptic neuron and being configured for providing an output signal (IBE) to the post-synaptic neuron,
• wherein the transistor structure is further configured to receive a retroaction signal (VFG) generated from the post-synaptic neuron, and
• the memristor is configured to modify the resistance value (R) based on a delay (Δt) between two at least partially overlapped input pulses, a spike event (FE1) of the first signal (VTE) and a pulse (VFGMAX) of the retroaction signal (VFG), in order to induct a potentiated state (STP) upon a decreasing the resistance value (R) and a depressed state (STD) upon increasing the resistance value (R) at the memristor, and
• wherein the transistor structure comprises a first transistor and a second transistor that are connected in parallel and are interposed between a first inner node and a second inner node, the first transistor has a control terminal coupled to the pre-synaptic neuron for receiving the second signal (VCG) and the second transistor has a control terminal connected to the post-synaptic neuron for receiving the retroaction signal (VFG), and
• wherein the memristor is a two-terminals memristor interposed between the first input terminal and the first inner node of the transistor structure.

A method of performing spike timing dependent plasticity (STDP) by a synaptic circuit comprising a memristor having a variable resistance value (R), the memristor being interposed between a pre-synaptic neuron and a post-synaptic neuron, the method comprising:

• receiving a first signal (VTE) from the pre-synaptic neuron;
• receiving a retroaction signal (VFG) from the post-synaptic neuron, and modifying the resistance value (R) based on a delay (Δt) between two at least partially overlapped input pulses, a spike event (FE1) of the first signal (VTE) and a pulse (VFGMAX) of the retroaction signal (VFG), by inducting a potentiated state (STP) upon a decreasing the resistance value (R) and a depressed state (STD) upon increasing the resistance value (R) at the memristor (10);
• providing the synaptic circuit comprising a two terminals memristor;
• connecting a transistor structure in series with the memristor;
• receiving at the memristor the first signal (VTE);
• receiving at the transistor structure a second signal (VCG) from the pre-synaptic neuron;
• providing an output signal (IBE) to the post-synaptic neuron by the intermediate unit;
• receiving the retroaction signal (VFG) at the transistor structure;
• providing the transistor structure by comprising a first transistor and a second transistor;
• connecting the second transistor in parallel with the first transistor interposed between a first inner node and a second inner node;
• connecting the memristor to the first inner node;
• and
• connecting the post-synaptic neuron to the second node by an output terminal.