US 10,650,301 B2Granted

Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation

AssigneeInternational Business Machines Corporation

InventorsRodrigo Alvarez-Icaza Rivera, Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada

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Abstract

Embodiments of the invention provide a neurosynaptic system comprising a delay unit for receiving and buffering axonal inputs, and a neural computation unit for generating neuronal outputs by performing a set of computations based on at least one axonal input received by the delay unit. The system further comprises a permutation unit for receiving external inputs to the system, and transmitting external outputs from the system. The permutation unit maps each external input received as either an axonal input to the delay unit or an external output from the system. The permutation unit maps each neuronal output generated by the neural computation unit as either an axonal input to the delay unit or an external output from the system. The neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the neurons with the axons.

Claims16

Dependent claims

A neurosynaptic system comprising:

a neural computation unit comprising multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the multiple electronic neurons with the multiple electronic axons, wherein the neural computation unit is configured to perform a set of computations based on one or more axonal inputs and a first neural computation matrix to generate one or more neuronal outputs;
a scheduler delay buffer configured to receive and buffer the one or more axonal inputs;
and
a packet router configured to:
receive one or more external inputs from an environment external to the neurosynaptic system, each external input comprising a sensory input;
transmit one or more external outputs to the environment external to the neurosynaptic system, each external output comprising a motor output;
selectively route the one or more external inputs based on a first routing permutation matrix, each external input routed to one of:
the scheduler delay buffer as one of the one or more axonal inputs, or the environment external to the neurosynaptic system as one of the one or more external outputs;
and
selectively route the one or more neuronal outputs based on the first routing permutation matrix, each neuronal output routed to one of:
the scheduler delay buffer as an axonal input, or the environment external to the neurosynaptic system as one or the one or more external outputs;
wherein the first neural computation matrix represents a concatenation of multiple neural computation matrices implemented by multiple layers of neurosynaptic core circuits;
wherein the first routing permutation matrix represents a concatenation of multiple routing permutation matrices implemented by the multiple layers;
and
wherein the multiple layers is a hybrid of a fully feed-forward configuration and a fully recurrent configuration.

12 more elements

A method comprising:

receiving and buffering one or more axonal inputs in a scheduler delay buffer of a neurosynaptic system;
generating one or more neuronal outputs by performing a set of computations based on the one or more axonal inputs and a first neural computation matrix utilizing a neural computation unit of the neurosynaptic system, wherein the neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the multiple electronic neurons with the multiple electronic axons;
receiving, via a packet router of the neurosynaptic system, one or more external inputs from an environment external to the neurosynaptic system, wherein each external input comprises a sensory input;
transmitting, via the packet router, one or more external outputs to the environment external to the neurosynaptic system, wherein each external output comprises a motor output;
selectively routing, via the packet router, the one or more external inputs based on a first routing permutation matrix, wherein each external input is routed to one of:
the scheduler delay buffer as one of the one or more axonal inputs, or the environment external to the neurosynaptic system as one of the one or more external outputs;
and
selectively routing, via the packet router, the one or more neuronal outputs based on the first routing permutation matrix, wherein each neuronal output is routed to one of:
the scheduler delay buffer as an axonal input, or the environment external to the neurosynaptic system as one or the one or more external outputs;
wherein the first neural computation matrix represents a concatenation of multiple neural computation matrices implemented by multiple layers of neurosynaptic core circuits;
wherein the first routing permutation matrix represents a concatenation of multiple routing permutation matrices implemented by the multiple layers;
and
wherein the multiple layers is a hybrid of a fully feed-forward configuration and a fully recurrent configuration.

10 more elements

A computer program product for computing computational functions, the computer program product comprising a non-transitory computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to:

receiving and buffering one or more axonal inputs in a scheduler delay buffer of a neurosynaptic system;
generating one or more neuronal outputs by performing a set of computations based on the one or more axonal inputs and a first neural computation matrix utilizing a neural computation unit of the neurosynaptic system, wherein the neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the multiple electronic neurons with the multiple electronic axons;
receiving, via a packet router of the neurosynaptic system, one or more external inputs from an environment external to the neurosynaptic system, wherein each external input comprises a sensory input;
transmitting, via the packet router, one or more external outputs to the environment external to the neurosynaptic system, wherein each external output comprises a motor output;
selectively routing, via the packet router, the one or more external inputs based on a first routing permutation matrix, wherein each external input is routed to one of:
the scheduler delay buffer as one of the one or more axonal inputs, or the environment external to the neurosynaptic system as one of the one or more external outputs;
and
selectively routing, via the packet router, the one or more neuronal outputs based on the first routing permutation matrix, wherein each neuronal output is routed to one of:
the scheduler delay buffer as an axonal input, or the environment external to the neurosynaptic system as one or the one or more external outputs;
wherein the first neural computation matrix represents a concatenation of multiple neural computation matrices implemented by multiple layers of neurosynaptic core circuits;
wherein the first routing permutation matrix represents a concatenation of multiple routing permutation matrices implemented by the multiple layers;
and
wherein the multiple layers is a hybrid of a fully feed-forward configuration and a fully recurrent configuration.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/273,487Filed 8 May 2014
Published: US 2015/0324684 A112 Nov 2015
Granted: 12 May 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06N 3/0499
Architecture, e.g. interconnection topology: feedforward networks
G06N 3/049
Architecture, e.g. interconnection topology: temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
G06N
AI and machine learning