US 10,650,112 B1 · Multi-bit clock gating cell to reduce clock power

Abstract

Systems, apparatuses, and methods for efficiently implementing clock gating circuitry. A multi-bit clock gating cell is placed on the die of an integrated circuit and replaces at least two single-bit clock gating cells that were to be placed on the die. Each single-bit clock gating cell receives a single clock enable signal and generates a single gated clock signal. Each multi-bit clock gating cell receives multiple clock enable signals and generates multiple gated clock signals based on a single common received clock signal. Conditions for determining whether two or more single-bit clock gating cells are replaced by a multi-bit clock gating cell include a distance between two single-bit clock gating cells, a load driven by any one of the two single-bit clock gating cells and an activity level of a common single clock received by at least two single-bit clock gating cells is above a respective threshold.

Claims20

Dependent claims

A clock gating circuit comprising:

circuitry configured to receive a single input clock signal;
a plurality of latches, each configured to:
receive one of a plurality of clock enable signals;
receive a clock signal corresponding to the single input clock signal;
and
generate one of a plurality of control signals;
and
a plurality of clock buffers, each configured to:
generate a different output clock signal based on the input clock signal and a different one of the plurality of control signals;
and
send one or more of the different output clock signals to one or more external clock buffers.

8 more elements

A method comprising:

identifying a first clock enable signal received by a first single-bit clock gating cell at a given level of a clock tree hierarchy of an integrated circuit;
identifying a second clock enable signal received by a second single-bit clock gating cell at the given level of the clock tree hierarchy;
in response to determining a distance between the first single-bit clock gating cell and the second single-bit clock gating cell exceeds a distance threshold, using the first single-bit clock gating cell and the second single-bit clock gating cell in the integrated circuit;
and
in response to determining the distance is below the distance threshold:
replacing the first single-bit clock gating cell and the second single-bit clock gating cell with a multi-bit clock gating cell in the integrated circuit;
and
combining the first clock enable signal and the second clock enable signal with a single common clock signal in the multi-bit clock gating cell.

5 more elements

A system for generating a layout of an integrated circuit, the system comprising:

a processor;
and
a non-transitory computer readable storage medium comprising program instructions operable to place and route clock gating circuits in an integrated circuit, wherein the program instructions when executed by the processor cause the system to:
identify a first clock enable signal received by a first single-bit clock gating cell at a given level of a clock tree hierarchy of an integrated circuit;
identify a second clock enable signal received by a second single-bit clock gating cell at the given level of the clock tree hierarchy;
in response to determining a distance between the first single-bit clock gating cell and the second single-bit clock gating cell exceeds a distance threshold, use the first single-bit clock gating cell and the second single-bit clock gating cell in the integrated circuit;
and
in response to determining at least the distance is below the distance threshold:
replace the first single-bit clock gating cell and the second single-bit clock gating cell with a multi-bit clock gating cell in the integrated circuit;
and
combine the first clock enable signal and the second clock enable signal with a single common clock signal in the multi-bit clock gating cell.

8 more elements

Dependencies are inferred from the claim text.

Multi-bit clock gating cell to reduce clock power

Life of this patent

Multi-bit clock gating cell to reduce clock power

Life of this patent

Abstract

Claims20