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US 10,649,944 B2Granted
Configuration via high speed serial link
AssigneeAltera Corporation
InventorsRamanand Venkata, Gopi Krishnamurthy
Life of this patent
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Abstract
Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.
Claims25
An integrated circuit, comprising:
- configuration memory that controls circuitry of a field programmable gate array (FPGA) fabric;
- a plurality of PCI Express blocks, wherein the plurality of PCI Express blocks are configured to receive operating data, and wherein the plurality of PCI Express blocks consists of a single PCI Express block configured to receive configuration data;
- configuration circuitry configured to receive the configuration data from the single PCI Express block and provide the configuration data to the configuration memory;
- and
- a dedicated link between the single PCI Express block and the configuration circuitry to transmit the configuration data from the single PCI Express block to the configuration circuitry, wherein the configuration data comprises instructions to configure the integrated circuit, and wherein the operating data comprises data communicated to the integrated circuit after the integrated circuit is configured using the configuration data.
2 more elements
A method comprising:
- receiving operating data at a field programmable gate array (FPGA) via a plurality of PCI Express blocks, wherein the plurality of PCI Express blocks are configured to receive the operating data, and wherein the plurality of PCI Express blocks consists of a single PCI Express block configured to receive configuration data;
- receiving configuration data at configuration circuitry via the single PCI Express block;
- sending the configuration data from the single PCI Express block to the configuration circuitry via a dedicated link that couples the configuration circuitry to a configuration memory to transmit the configuration data from the single PCI Express block to the configuration circuitry, wherein the configuration data comprises instructions received by the single PCI Express block to configure the FPGA, wherein the configuration memory controls circuitry of the FPGA;
- and
- upon configuring the FPGA, receiving the operating data, wherein the operating data comprises data communicated to the FPGA after the FPGA is configured using the configuration data.
2 more elements
A programmable logic device (PLD), comprising:
- a plurality of PCI Express blocks, wherein the plurality of PCI Express blocks are configurable to receive operating data, wherein the plurality of PCI Express blocks consists of only a single PCI Express block configurable to receive configuration data;
- configuration circuitry that receives the configuration data from the single PCI Express block and provides configuration instructions to configuration memory of the PLD to program the PLD;
- and
- a link that couples only the single PCI Express block to the configuration circuitry to transmit the configuration data from the single PCI Express block to the configuration circuitry, wherein the configuration data comprises instructions to configure the PLD, and wherein the operating data comprises data communicated to the PLD after the PLD is configured using the configuration data.
1 more element
A field programmable gate array (FPGA), comprising:
- a plurality of PCI Express blocks, wherein the plurality of PCI Express blocks are configurable to receive operating data such that the plurality of PCI Express blocks receive the operating data, and wherein the plurality of PCI Express blocks consists of only one PCI Express block configurable to receive configuration data;
- configuration circuitry that receives the configuration data from the one PCI Express block and provides configuration instructions to configuration memory of the FPGA to program the FPGA;
- and
- a dedicated link that couples the one PCI Express block to the configuration circuitry to transmit the configuration data from the one PCI Express block to the configuration circuitry, wherein the configuration data comprises the instructions to configure the FPGA, and wherein the operating data comprises data communicated to the FPGA after the FPGA is configured using the configuration data.
1 more element
Dependencies are inferred from the claim text.