System and method for I/O aware processor configuration

A method, comprising:

• connecting a first processor die of a plurality of processor dies of a processor of an information handling system to an input/output (I/O) device via a first serial interface of the first processor die, wherein the processor dies are configured in a non-uniform memory access architecture, and wherein the first processor die includes X processor cores, X being an integer number greater than one;
• coupling a second processor die of the processor dies to the first processor die, wherein the second processor die includes Y processor cores, Y being an integer number greater than one, and wherein the second processor die is not connected to the I/O device;
• determining, by the information handling system, that the first processor die is connected to the I/O device and that the second processor die is not connected to the I/O device;
• determining, by the information handling system, that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y;
• and
• enabling, by the information handling system, the Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z X, on the second processor die, based upon the determination that the second processor die is not connected to the I/O device.

An information handling system, comprising:

• an input/output (I/O) device;
• and
• a processor including a plurality of processor dies configured in a non-uniform memory access architecture, the processor dies including a first processor die having X processor cores and a first serial interface, wherein X is an integer number greater than one, and the first processor die is connected to the I/O device via the first serial interface, and the processor dies further including a second processor die including Y processor cores and a second serial interface, wherein Y is an integer number greater than one, the second processor die is coupled to the first processor die, and the second processor die is not connected to the I/O device via the second serial interface;
• and
• the processor configured to:
• determine that the first processor die is connected to the I/O device and that the second processor die is not connected to the I/O device;
• determine that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y;
• and
• enable Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z−X, on the second processor die, based upon the determination that the second processor die is not connected to the I/O device via the second serial interface.