Universal asynchronous receiver/transmitter unit, and memory controller and memory system including the same

A memory controller comprising:

• a host interface configured to receive an output command from a host;
• a flash translation layer (FTL) configured to provide output information in response to the output command, the output information including first and second information, the first information being one or more words;
• and
• a UART unit configured to receive the output information, store a plurality of word codes corresponding to a plurality of words, extract the first information from the output information, obtain one or more word codes corresponding to the first information among the plurality of word codes, generate an output code by combining the one or more word codes with the second information, and generate debugging information using the output code,
• wherein the UART unit includes:
• a WORD table configured to store text information including the plurality of words and the plurality of word codes corresponding to the text information;
• a UART controller configured to extract the one or more words from the output information, output the extracted one or more words to the WORD table, and generate the output code by combining the second information with the one or more word codes output from the WORD table;
• and
• a UART configured to output the debugging information using the output code.

A memory system comprising:

• a memory device configured to store data;
• and
• a memory controller configured to control the memory device in response to a request of a host, and output debugging information of output information in response to an output command received from the host, the output information including first and second information, the first information being one or more words,
• wherein the memory controller includes text information including a plurality of words and a plurality of word codes corresponding to the text information, and outputs the debugging information by extracting the first information from the output information, obtaining one or more word codes corresponding to the first information from the plurality of word codes, and combining the one or more word codes with the second information in response to the output command,
• wherein the memory controller includes:
• a WORD table configured to store the plurality of words of the text information and the plurality of word codes corresponding to the plurality of words;
• a UART controller configured to extract the one or more words from the output information, output, to the WORD table, the extracted one or more words, receive the one or more word codes from the WORD table, and generate an output code by combining the one or more word codes with the second information;
• and
• a UART configured to output the debugging information using the output code.