US 10,649,925 B2 · Indirect data return from memory controller logic

Abstract

A portion of the memory space, supported by memory chips that are being controlled by a memory controller logic, can be set aside and read requests directed to memory addresses within that portion can be redirected, by the memory controller logic, to other memory addresses at which is stored the data equivalent to the internal data of the memory controller logic that the memory controller logic seeks to return, thereby enabling the memory controller logic to indirectly return data to processes executing on the host computing device. Additionally, requests to write data to specific memory addresses, including memory addresses that can be within the set aside portion, can be interpreted, by the memory controller logic, as commands that the memory controller logic is to perform, and which impact its own internal data including commands to reset values, or start or end data collection, or other like commands.

Claims20

Dependent claims

A method for enabling memory controller logic to externally communicate internal data, the method comprising:

receiving a request to read data stored at a first memory location;
establishing a communicational path to the first memory location, thereby enabling a reading of a first data stored at the first memory location, if the first memory location is not within a first subset of memory locations;
identifying, if the first memory location is within the first subset of memory locations, a second memory location, differing from the first memory location, at which is stored a second data that is equivalent to the internal data that is to be externally communicated, the identifying being based on the second data, already stored at the second memory location, being equivalent to the internal data that is to be externally communicated;
and
responding to the request to read the first memory location by establishing a communicational path to the second memory location, thereby enabling a reading of the second data stored at the second memory location if the first memory location is within the first subset of memory locations.

2 more elements

A register clock driver (RCD) chip comprising:

internal memory storing a first data;
and
a processing unit which, when executing, performs steps comprising:
receive a request to read data stored at a first memory location, the first memory location being on a memory chip external to the RCD, the RCD controlling read and write access to the memory chip;
establish a communicational path to the first memory location, thereby enabling a reading of a first data stored at the first memory location, if the first memory location is not within a first subset of memory locations;
identify, if the first memory location is within the first subset of memory locations, a second memory location, differing from the first memory location, at which is stored a second data that is equivalent to the first data stored in the internal memory of the RCD, the identifying being based on the second data, already stored at the second memory location, being equivalent to the first data stored in the internal memory of the RCD;
and
respond to the request to read the first memory location by establishing a communicational path to the second memory location, thereby enabling a reading of the data stored at the second memory location if the first memory location is within the first subset of memory locations.

5 more elements

A computing device comprising:

one or more central processing units (CPUs);
random access memory (RAM);
a register clock driver (RCD) chip controlling read and write access to the RAM and comprising internal memory storing a first data;
and
one or more computer-readable media comprising computer-executable instructions, which, when executed by the one or more CPUs, cause the one or more CPUs to issue a request to read data stored at a first memory location;
wherein, if the first memory location is not within a first subset of memory locations, the RCD chip establishes a communicational path between the one or more CPUs and a portion of the RAM corresponding to the first memory location, thereby enabling the one or more CPUs to read a first data stored at the first memory location;
and
wherein further, if the first memory location is within the first subset of memory locations, the RCD chip identifies a second memory location, differing from the first memory location, at which is stored a second data that is equivalent to the first data stored in the internal memory of the RCD and responds to the request to read the first memory location by establishing a communicational path to the second memory location, the identifying being based on the second data, already stored at the second memory location, being equivalent to the first data stored in the internal memory of the RCD.

5 more elements

Dependencies are inferred from the claim text.

Indirect data return from memory controller logic

Life of this patent

Indirect data return from memory controller logic

Life of this patent

Abstract

Claims20