Dynamic reconfiguration and management of memory using field programmable gate arrays

A method for managing memory hot-add to a computing platform, the method comprising:

• training of a memory module, by a Memory Reference Code (MRC) Register Transfer Level (RTL) module of a Field Programmable Gate Array (FPGA) memory controller circuit (FMC circuit), in response to receiving a memory hot-add event notification associated with the memory module, wherein the MRC training includes adjusting of memory read timing and write timing based on configuration policies, through which improved read and write timing for hot-add versus host access is obtained for the memory module;
• and
• communicating, by a management controller circuit, with a remote administration server over a secure out-of-band network channel, the communicating including transmission of the configuration policies to be applied by the FMC circuit to the memory module.

At least one non-transitory computer readable storage medium having instructions encoded thereon that, when executed by one or more processors, result in operations for managing memory hot-add to a computing platform, the operations comprising:

• performing Memory Reference Code (MRC) training of a memory module in response to receiving a memory hot-add event notification associated with the memory module, wherein the MRC training includes adjusting of memory read timing and write timing based on configuration policies, through which improved read and write timing for hot-add versus host access is obtained for the memory module;
• and
• communicating with a remote administration server over a secure out-of-band network channel, the communicating including transmission of the configuration policies to be applied to the memory module.