Storage in a non-volatile memory
AssigneesSTMicroelectronics (Rousset) SAS, Proton World International N.V.
InventorsMichael Peeters, Fabrice Marinet, Jean-Louis Modave
Life of this patent
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Abstract
A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.
Claims19
A method, comprising:
- scrambling, using scrambling circuitry of a non-volatile memory organized in pages and having a word writing granularity of one or more bytes and a block erasing granularity of one or more pages, logical addresses into physical addresses, by:
- scrambling logical data addresses based on a page structure of the non-volatile memory, wherein scrambling a data address includes modifying a set of least significant bits representative of the data address without modifying bits representative of a page of the data address;
- and
- scrambling logical code addresses based on a word structure of the non-volatile memory, wherein the scrambling of logical data addresses is different from the scrambling of logical code addresses, the blocks are organized into groups of blocks and scrambling a code address includes modifying a set of least significant bits representative of the code address without modifying bits representative of an address of a group of blocks;
- and
- performing memory operations based on the physical addresses.
A circuit, comprising:
- at least one non-volatile memory organized in pages and having a word writing granularity of one or more bytes and a block erasing granularity of one or more pages;
- and
- scrambling circuitry coupled to the non-volatile memory and which, in operation, converts logical addresses into physical addresses, by:
- scrambling logical data addresses based on a page structure of the non-volatile memory, wherein scrambling a data address includes modifying a set of least significant bits representative of the data address without modifying bits representative of a page of the data address;
- and
- scrambling logical code addresses based on a word structure of the non-volatile memory, wherein the scrambling of logical data addresses is different from the scrambling of logical code addresses, the blocks are organized into groups of blocks and scrambling a code address includes modifying a set of least significant bits representative of the code address without modifying bits representative of an address of a group of blocks.
A non-transitory, computer-readable medium having contents which cause a scrambling circuit of a non-volatile memory to scramble logical addresses into physical addresses, the non-volatile memory being organized in pages and having a word writing granularity of one or more bytes and a block erasing granularity of one or more pages, the scrambling comprising:
- scrambling logical data addresses based on a page structure of the non-volatile memory, wherein scrambling a data address includes modifying a set of least significant bits representative of the data address without modifying bits representative of a page of the data address;
- and
- scrambling logical code addresses based on a word structure of the non-volatile memory, wherein operations in the non-volatile memory are performed using the physical addresses, the scrambling of logical data addresses is different from the scrambling of logical code addresses, the blocks are organized into groups of blocks and scrambling a code address includes modifying a set of least significant bits representative of the code address without modifying bits representative of an address of a group of blocks.
A system, comprising:
- data processing circuitry;
- a non-volatile memory organized in pages and having a word writing granularity of one or more bytes and a block erasing granularity of one or more pages;
- and
- scrambling circuitry, coupled between the data processing circuitry and a decoder of the non-volatile memory, wherein the scrambling circuitry, in operation, converts logical addresses into physical addresses, by:
- scrambling logical data addresses based on a page structure of the non-volatile memory, wherein scrambling a data address includes modifying a set of least significant bits representative of the data address without modifying bits representative of a page of the data address;
- and
- scrambling logical code addresses based on a word structure of the non-volatile memory, wherein the scrambling of logical data addresses is different from the scrambling of logical code addresses, the blocks are organized into groups of blocks and scrambling a code address includes modifying a set of least significant bits representative of the code address without modifying bits representative of an address of a group of blocks.
Dependencies are inferred from the claim text.