Method and apparatus for an efficient TLB lookup
AssigneeInternational Business Machines Corporation
InventorsMichael Johannes Jaspers, Markus Kaltenbach, Girish G. Kurup, Ulrich Mayer
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Abstract
The present disclosure relates to a method of operating a translation lookaside buffer (TLB) arrangement for a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units. The method comprises: maintaining by a cache unit a dependency matrix for the engines to track for each processing unit if an engine is assigned to the each processing unit for a table walk. The cache unit may block a processing unit from allocating an engine to a translation request when the engine is already assigned to the processing unit in the dependency matrix.
Claims13
An apparatus for operating a translation lookaside buffer (TLB) arrangement, of a processor supporting virtual addressing, wherein multiple translation engines are used to perform translations on request of one of a plurality of dedicated processor units, the apparatus being configured for:
- maintaining by a cache unit a dependency matrix for the multiple translation engines to track for each processing unit if a translation engine of the multiple translation engines is assigned to each processing unit for a table walk;
- and
- blocking by the cache unit a processing unit from allocating one of the multiple translation engines to a translation request when one of the multiple translation engines is already assigned to the processing unit in the dependency matrix, and
- wherein the TLB arrangement comprises at least two translation lookaside buffers of which a first one (TLB1) is a first level buffer maintained by the cache unit and a second one (TLB2) is a second level translation lookaside buffer arranged to feed said first one with address information in case of a missing address of the first one and maintained by the processing unit, wherein the translation request is executed on the first level TLB1 and on the second level TLB2, wherein in response to a TLB miss in the first level TLB1 initiating by the cache unit a further translation request.
A computer program product comprising a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code configured to implement the steps of:
- maintaining by a cache unit a dependency matrix for the multiple translation engines to track for each processing unit if a translation engine of the multiple translation engines is assigned to each processing unit for a table walk;
- and
- blocking by the cache unit a processing unit from allocating one of the multiple translation engines to a translation request when one of the multiple translation engines is already assigned to the processing unit in the dependency matrix, and
- wherein the TLB arrangement comprises at least two translation lookaside buffers of which a first one (TLB1) is a first level buffer maintained by the cache unit and a second one (TLB2) is a second level translation lookaside buffer arranged to feed said first one with address information in case of a missing address of the first one and maintained by the processing unit, wherein the translation request is executed on the first level TLB1 and on the second level TLB2, wherein in response to a TLB miss in the first level TLB1 initiating by the cache unit a further translation request.
Dependencies are inferred from the claim text.