Supporting memory paging in virtualized systems using trust domains
AssigneeIntel Corporation
InventorsHormuzd M. Khosravi, Baiju Patel, Ravi Sahita, Barry Huntley
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AssigneeIntel Corporation
InventorsHormuzd M. Khosravi, Baiju Patel, Ravi Sahita, Barry Huntley
Estimating the term…
Embodiment of this disclosure provide techniques to support full memory paging between different trust domains (TDs) in compute system without losing any of the security properties, such as tamper resistant/detection and confidentiality, on a per TD basis. In one embodiment, a processing device including a memory controller and a memory paging circuit operatively coupled to the memory controller is provided. The memory paging circuit is to evict a memory page associated with a trust domain (TD) executed by the processing device. A binding of the memory page to a first memory location of the TD is removed. A transportable page that includes encrypted contents of the memory page is created. Thereupon, the memory page is provided to a second memory location.
A processing device comprising:
A method comprising:
A system comprising:
Dependencies are inferred from the claim text.