System and method for store streaming detection and handling
AssigneeSamsung Electronics Co., Ltd.
InventorsHao Wang, Dilip Muthukrishnan, Brian C. Grayson
Life of this patent
Estimating the term…
Abstract
According to one general aspect, an apparatus may include a load/store circuit and a region size detection circuit. The load/store circuit may be configured to issue a plurality of store instructions to store data in a memory system. The region size detection circuit may be configured to determine a cache from a plurality of caches to store a stream of store instructions based upon, at least in part, by tracking multiple cache-line address entries in the plurality of store instructions, wherein each address entry is updated at a different frequency.
Claims20
An apparatus comprising:
- a store circuit configured to issue a plurality of store instructions to store data in a memory system;
- and
- a region size detection circuit configured to determine a cache, from within a cache system of a processor that includes a plurality of caches, to store data associated with a stream of store instructions based upon, at least in part, by tracking multiple cache-line address entries associated with the plurality of store instructions, wherein each respective cache-line address entry is updated at a frequency based, at least in part, upon a size of a cache associated with a respective cache-line address entry and a number associated with the plurality of store instructions, wherein the region size detection circuit comprises an address entry table having the multiple cache-line entries.
A method comprising:
- receiving a plurality of store instructions to store data in a memory system of a processor, wherein the memory system is configured to, at least temporarily, store the data in at least one cache;
- and
- selecting, via a region size detection circuit, a cache within a tiered cache system of the memory system of the processor to store the data associated with a stream of store instructions based upon, at least in part, by tracking multiple address entries associated with the plurality of store instructions, wherein each address entry is updated at a frequency based, at least in part, upon a number of store instructions, wherein the region size detection circuit comprises an address entry table having the multiple address entries.
Dependencies are inferred from the claim text.