Memory device including detection clock pattern generator for generating detection clock output signal including random data pattern

A memory device comprising:

• an output pin;
• a mode register;
• and
• a signal generator configured to generate training data comprising a random data pattern in response to a first control signal output from the mode register during a first mode, and output the training data through the output pin at one of a first rate and a second rate different from the first rate based on a second control signal output from the mode register,
• wherein the random data pattern includes pseudo-random data generated by the memory device, and
• wherein the training data is used for a clock and data recovery operation.

A memory device comprising:

• a first error detection code (EDC) pin;
• a second EDC pin;
• a signal generator configured to output a first detection clock signal comprising a first random data pattern through the first EDC pin and output a second detection clock signal comprising a second random data pattern through the second EDC pin, during a first period;
• calculate first cyclic redundancy check (CRC) data based on first data;
• calculate second CRC data based on second data;
• and output the first CRC data through the first EDC pin and the second CRC data through the second EDC pin, during a second period after the first period, wherein the first and second random data patterns include pseudo-random data generated by the memory device, and wherein the random data patterns are used for a clock data recovery operation,
• wherein the signal generator outputs the detection clock output signals through the EDC pins at one of a first rate and a second rate different from the first rate based on a control signal output from a mode register of the memory device.