Processor and memory access method

A memory access method by a memory controller that controls an access to a memory which comprises a plurality of through electrode groups and a memory chip including a plurality of storage areas connected to the plurality of through electrode groups, each of the through electrode groups including a plurality of through electrodes, the method comprising:

• outputting an access address included in a read access request, as an error address, by an address-filter circuit of the memory controller in when a response output from the memory, in response to the read access request of reading data from the memory, includes error information indicating that an error in the data has been corrected in the memory and when it is determined that the error in the data at the access address included in the read access request has been corrected for a first time, the address-filter circuit comprises:
• a holding circuit that holds the access address, and
• an output control circuit that outputs the error address to the counter and stores the error address in the holding circuit in a case where the response to the read access request includes the error information and an access address included in the response to the read access request is not held in the holding circuit, and that hinders an output of the error address to the counter in a case where the response to the read access request includes the error information and the access address included in the response to the read access request is held in the holding circuit;
• updating a counter value of a counter corresponding to the through electrode group connected to the storage area indicated by the received error address among a plurality of counters provided to respectively correspond to the plurality of through electrode groups, by a counter of the memory controller;
• outputting area information by an area-information-output circuit of the memory controller, the area information indicating the storage area connected to the through electrode group corresponding to the counter having a counter value which is greater than a predetermined value;
• and
• outputting, to the memory with a predetermined time gap from an issuing circuit of the memory controller, an access request to the storage area indicated by the area information output from the area-information-output circuit and an access request to the storage area adjacent to the storage area indicated by the area information output from the area-information-output circuit, to the memory with a predetermined time gap by an issuing circuit of the memory controller.