Reduced stack usage in a multithreaded processor

A method performed by a multithreaded processor executing a plurality of threads, the method comprising:

• receiving a procedure entry instruction at instruction decode logic of the multithreaded processor, the procedure entry instruction corresponding to a first thread of the plurality of threads and to a stack associated with the first thread;
• retrieving a value of a first stack limit enable bit of a plurality of stack limit enable bits stored in a second control register of the multithreaded processor, wherein each stack limit enable bit of the plurality of stack limit enable bits corresponds to a respective thread of the plurality of threads, and wherein the first stack limit enable bit is associated with the first thread;
• and
• accessing, when the value indicates that the first stack limit enable bit is in a first state, a first control register of the multithreaded processor to retrieve a stack limit value;
• and
• responsive to the first stack limit enable bit being in the first state, determining whether to throw a stack limit exception based on the stack limit value and a first predefined stack region size associated with the procedure entry instruction,
• wherein, when the value indicates that the first stack limit enable bit is in a second state, the instruction decode logic is configured to execute the procedure entry instruction without retrieving the stack limit value.

A system comprising:

• a multithreaded processor configured to execute a plurality of threads, wherein the multithreaded processor comprises a first control register configured to store a stack limit value, and a second control register configured to store a plurality of stack limit enable bits, and wherein each stack limit enable bit of the plurality of stack limit enable bits corresponds to a respective thread of the plurality of threads;
• and
• a memory coupled with the multithreaded processor and comprising:
• a plurality of first memory pages, each first memory page comprising a first plurality of memory regions each having a first predefined stack region size, a first stack assigned to a first memory region of the first plurality of memory regions, the first stack corresponding to a first thread of the plurality of threads;
• and
• a plurality of second memory pages, each second memory page comprising a second plurality of memory regions each having a second predefined stack region size greater than the first predefined stack region size, wherein the multithreaded processor is configured to:
• determine, responsive to receiving a first procedure entry instruction for the first stack, that a first stack limit enable bit of the plurality of stack limit enable bits is in a set state, wherein the first stack limit enable bit is associated with the first thread;
• check the stack limit value responsive to the first stack limit enable bit;
• throw a stack limit exception responsive to the stack limit value;
• reassign, responsive to throwing the stack limit exception, the first stack to a second memory region of the second plurality of memory regions;
• clear the first stack limit enable bit responsive to reassigning the first stack to the second memory region;
• and
• responsive to receiving a second procedure entry instruction associated with the first thread, execute the second procedure entry instruction without checking the stack limit value.

A method performed by a multithreaded processor executing a plurality of threads, the multithreaded processor coupled with a memory comprising a plurality of first memory pages, each first memory page comprising a first plurality of memory regions each having a first predefined stack region size, a first stack assigned to a first memory region of the first plurality of memory regions, the first stack corresponding to a first thread of the plurality of threads, the method comprising:

• determining, responsive to receiving a first procedure entry instruction for the first stack, that a first stack limit enable bit is in a set state, the first stack limit enable bit of a plurality of stack limit enable bits stored in a control register of the multithreaded processor, wherein the first stack limit enable bit is associated with the first thread;
• checking a stack limit value responsive to the first stack limit enable bit;
• throwing a stack limit exception responsive to the stack limit value;
• reassigning, responsive to throwing the stack limit exception, the first stack to a second memory region within the memory, the memory further comprising a plurality of second memory pages, each second memory page comprising a second plurality of memory regions each having a second predefined stack region size greater than the first predefined stack region size;
• clearing the first stack limit enable bit responsive to reassigning the first stack to the second memory region;
• and
• responsive to receiving a second procedure entry instruction associated with the first thread, executing the second procedure entry instruction without checking the stack limit value.