Multicore system for fusing instructions queued during a dynamically adjustable time window

A processor comprising a plurality of cores, each comprising:

• a fetch circuit to fetch instructions, each instruction to specify an opcode;
• an instruction queue (IQ) to enqueue fetched instructions;
• a decode circuit to decode enqueued instructions;
• an execution circuit to execute decoded instructions;
• and
• an instruction fusion circuit to fuse a first enqueued instruction and a second enqueued instruction to form a fused instruction to be decoded by the decode circuit as a single instruction instead of the first and second enqueued instructions being decoded separately, the instruction fusion circuit determining to fuse the first and second enqueued instructions based on their specified opcodes;
• wherein the instruction fusion circuit is to determine to fuse the first and second enqueued instructions after the first and second enqueued instructions have been fetched, and before the first and second enqueued instructions are decoded, and
• wherein the instruction fusion circuit is further to delay issuance of the first enqueued instruction to the decode circuit for a threshold number of cycles in order to attempt to avoid missing an instruction-fusion opportunity, the threshold number of cycles to be dynamically adjusted in response to power and performance requirements by increasing the threshold to increase a likelihood of fusing instructions, thereby reducing power consumption and reducing performance.

A method performed by a processor core, the method comprising:

• fetching instructions using a fetch circuit, each instruction to specify an opcode;
• enqueuing fetched instructions using an instruction queue (IQ);
• decoding enqueued instructions using a decode circuit;
• executing decoded instructions using an execution circuit;
• and
• fusing, using an instruction fusion circuit, a first enqueued instruction and a second enqueued instruction to form a fused instruction to be decoded by the decode circuit as a single instruction instead of the first and second enqueued instructions being decoded separately, the instruction fusion circuit determining to fuse the first and second enqueued instructions based on their specified opcodes;
• wherein the instruction fusion circuit determines to fuse the first and second enqueued instructions after the first and second enqueued instructions have been fetched, and before the first and second enqueued instructions are decoded, and wherein the instruction fusion circuit further delays issuance of the first enqueued instruction to the decode circuit for a threshold number of cycles in order to attempt to avoid missing an instruction-fusion opportunity, the threshold number of cycles to be dynamically adjusted in response to power and performance requirements.