Enhanced performance-aware instruction scheduling

A method for instruction processing by a processor having multiple execution units, wherein the processor having multiple execution units comprises a dependency cache containing instructions associated with respective execution unit indicators, and wherein an execution unit indicator identifies an execution unit, of the multiple execution units, on which an instruction, of the instructions, is planned to be executed on, and wherein the respective execution unit indicators are stored with the instructions, the method comprising:

• tracking dependent instructions currently assigned to each respective execution unit of the processor;
• in response to receiving an instruction of a dependency chain, identifying in the dependency cache the execution unit assigned to a previous instruction of the dependency chain on which the received instruction depends;
• and
• in response to more than a predefined maximum number of dependent instructions of the dependency chain are currently assigned to the identified execution unit, selecting another execution unit of the processor having multiple execution units for scheduling the received instruction.