Data processing apparatus and method for executing a stream of instructions out of order with respect to original program order

A method of executing a stream of instructions out of order with respect to original program order within a data processing apparatus, said stream of instructions including instructions that identify one or more architectural registers from a set of architectural registers, the method comprising:

• employing a plurality of out of order components to manage execution of a first subset of said instructions out of order, said plurality of out of order components configured to remove false dependencies between instructions in said first subset, and said plurality of out of order components including a first issue queue into which the instructions in said first subset are buffered prior to execution;
• employing a second issue queue into which a second subset of said instructions are buffered prior to execution, said second subset of instructions being constrained to execute in order;
• sectioning the stream of instructions into a plurality of instruction runs, each instruction run comprising a block of instructions in original program order comprising one or more instructions in said first subset followed by one or more instructions in said second subset, referencing both the first issue queue and the second issue queue in order to determine an order of execution of instructions from both the first and second issue queues, constraining the order of execution of said first subset of instructions only by true dependencies between the instructions in both the first and second issue queues, and constraining the order of execution of said second subset of instructions by both the true dependencies and the false dependencies between the instructions in both the first and second issue queues,
• providing a run management table maintaining data associated with each instruction run that is referenced to determine for each instruction in said second issue queue, when one or more false dependencies no longer exist;
• and
• maintaining in the run management table a count value for each instruction run, as each instruction in the first subset is buffered in the first issue queue, adjusting the count value for a corresponding instruction run in a first direction, and as each instruction is issued from the first issue queue for execution, adjusting the count value for the corresponding instruction run in a second direction, and preventing an instruction in said second issue queue being issued for execution whilst the count value for the corresponding instruction run does not have a predetermined value, wherein the predetermined value indicates absence of the one or more false dependencies.

A data processing apparatus for executing a stream of instructions out of order with respect to original program order, said stream of instructions including instructions that identify one or more architectural registers from a set of architectural registers, the data processing apparatus comprising:

• a plurality of out of order component means for managing execution of a first subset of said instructions out of order, said plurality of out of order component means for removing false dependencies between instructions in said first subset;
• said plurality of out of order component means including a first issue queue means into which the instructions in said first subset are buffered prior to execution;
• a second issue queue means into which a second subset of said instructions are buffered prior to execution, said second subset of instructions being constrained to execute in order;
• and
• issue control means for referencing both the first issue queue means and the second issue queue means in order to determine an order of execution of instructions from both the first and second issue queue means, the issue control means further for constraining the order of execution of said first subset of instructions only by true dependencies between the instructions in both the first and second issue queue means, and for constraining the order of execution of said second subset of instructions by both the true dependencies and the false dependencies between the instructions in both the first and second issue queue means,
• wherein:
• the stream of instructions is sectioned into a plurality of instruction runs, each instruction run comprising a block of instructions in original program order comprising one or more instructions in said first subset followed by one or more instructions in said second subset, and the issue control means comprises a run management table maintaining data associated with each instruction run that is referenced by the issue control means to determine for each instruction in said second issue queue means, when one or more false dependencies no longer exist, and the run management table comprises a count value for each instruction run, as each instruction in the first subset is buffered in the first issue queue means, the count value for a corresponding instruction run being adjusted in a first direction, and as each instruction is issued from the first issue queue means for execution, the count value for the corresponding instruction run being adjusted in a second direction, and the issue control means being configured to prevent an instruction in said second issue queue means being issued for execution whilst the count value for the corresponding instruction run does not have a predetermined value, wherein the predetermined value indicates absence of the one or more false dependencies.