Multiplication instruction for which execution completes without writing a carry flag

A processor comprising:

• a flags register to store arithmetic flags;
• a decoder to decode instructions, including an unsigned multiply instruction;
• and
• execution circuitry coupled to the decoder, the execution circuitry to perform operations associated with the unsigned multiply instruction, the operations comprising to perform a multiplication of an unsigned explicit source operand and an unsigned implicit source operand to generate an unsigned product,
• the execution circuitry to store a lower half of the unsigned product in a first destination register and to store an upper half of the unsigned product in a second destination register without affecting any of the arithmetic flags, wherein the arithmetic flags include a carry flag and an overflow flag, and wherein the flags register is to additionally store a parity flag, an auxiliary carry flag, a zero flag, a sign flag, a trap flag, an interrupt enable flag, an I/O privileged level, a nested task flag, a resume flag, a virtual-8086 mode flag, an alignment check flag, a virtual interrupt flag, a virtual interrupt pending flag, an ID flag, and a direction flag.

A method comprising:

• writing arithmetic flags in a flags register and writing an alignment check flag;
• decoding instructions, including an unsigned multiply instruction;
• performing operations associated with the unsigned multiply instruction, the operations comprising performing a multiplication of an unsigned explicit source operand and an unsigned implicit source operand to generate an unsigned product;
• storing a lower half of the unsigned product in a first destination register;
• storing an upper half of the unsigned product in a second destination register;
• and
• completing performance of the unsigned multiply instruction without affecting any of the arithmetic flags.

An article of manufacture comprising a machine-readable storage medium, the machine-readable storage medium comprising at least one of an optical disk, a magnetic disk, a read only memory (ROM), and a random access memory (RAM), the machine-readable storage medium storing a set of instructions including an unsigned multiply instruction, the set of instructions when performed by a machine are to cause the machine to perform operations comprising to write arithmetic flags, an auxiliary carry flag, and a virtual interrupt pending flag in a flags register, and the unsigned multiply instruction when performed by a machine is to cause the machine to perform operations comprising to:

• decode the unsigned multiply instruction;
• perform operations associated with the unsigned multiply instruction, the operations including to perform a multiplication of an unsigned explicit source operand and an unsigned implicit source operand to generate an unsigned product;
• store a lower half of the unsigned product in a first destination register;
• store an upper half of the unsigned product in a second destination register;
• and
• complete the performance of the unsigned multiply instruction without affecting any of the arithmetic flags.

A processor comprising:

• a flags register to store arithmetic flags;
• a decoder to decode instruction, including an unsigned multiply instruction;
• and
• execution circuitry coupled to the decoder, the execution circuitry to perform operations associated with the unsigned multiply instruction, the operations comprising to perform a multiplication of an unsigned explicit source operand having a first number of bits and an unsigned implicit source operand having the first number of bits to generate an unsigned product having twice the first number of bits, wherein, if a first destination indicated by the unsigned multiply instruction, and a second destination indicated by the unsigned multiply instruction, are both a given register of the first number of bits, then a highest order half of the unsigned product is to be stored in the given register of the first number of bits, and a lowest order half of the unsigned product is not to be stored,
• wherein the arithmetic flags include a carry flag and an overflow flag, wherein the unsigned multiply instruction comprises an enable flag update control bit set to a first value to indicate that the carry flag and the overflow flag are not to be updated, and wherein the processor has a nested task flag.