US 10,649,772 B2 · Method and apparatus for efficient matrix transpose

Abstract

Disclosed embodiments relate to a method and apparatus for efficient matrix transpose. In one example, a processor to execute a matrix transpose instruction includes fetch circuitry to fetch the matrix transpose instruction specifying a destination matrix and a source matrix having (N×M) elements and (M×N) elements, respectively, a (N×M) load buffer, decode circuitry to decode the fetched matrix transpose instruction, and execution circuitry, responsive to the decoded matrix transpose instruction to, for each row X of M rows of the specified source matrix: fetch and buffer N elements of the row in a load register, and cause the N buffered elements to be written, in the same relative order as in the row, to column X of M columns of the load buffer, and the execution circuitry subsequently to write each of N rows of the load buffer to a same row of the load buffer.

Claims18

Dependent claims

A processor to execute a matrix transpose instruction, the processor comprising:

fetch circuitry to fetch the matrix transpose instruction specifying a destination matrix and a source matrix having (N×M) elements and (M×N) elements, respectively, the matrix transpose instruction further specifying M, N, and an element size being one of 1 byte, 2 bytes, 4 bytes, 8 bytes, and 16 bytes;
a (N×M) load buffer;
decode circuitry to decode the fetched matrix transpose instruction;
and
execution circuitry, responsive to the decoded matrix transpose instruction to, for each row X of M rows of the source matrix:
fetch and buffer N elements of the row in a load register distinct from the load buffer;
and
cause the N buffered elements to be written, in the same relative order as in the row, to column X of M columns of the load buffer;
and
the execution circuitry subsequently to write each of N rows of the load buffer to a same row of the destination matrix.

7 more elements

A method of executing a matrix transpose instruction by a processor, the method comprising:

fetching, using fetch circuitry, the matrix transpose instruction specifying a destination matrix and a source matrix having (N×M) elements and (M×N) elements, respectively, the matrix transpose instruction further specifying M, N, and an element size being one of 1 byte, 2 bytes, 4 bytes, 8 bytes, and 16 bytes;
decoding, using decode circuitry, the fetched matrix transpose instruction;
and
executing, using execution circuitry, responsive to the decoded matrix transpose instruction to, for each row X of M rows of the source matrix:
fetch and buffer N elements of the row in a load register;
and
cause the N buffered elements to be written, in the same relative order as in the row, to column X of M columns of a load buffer, the load buffer being distinct from the load register and having (N×M) elements;
and
the execution circuitry subsequently to write each of N rows of the load buffer to a same row of the destination matrix.

6 more elements

A non-transitory machine-readable medium containing instructions that, when executed by a processor, cause the processor to execute a matrix transpose instruction by:

fetching, using fetch circuitry, the matrix transpose instruction specifying a destination matrix and a source matrix having (N×M) elements and (M×N) elements, respectively, the matrix transpose instruction further specifying M, N, and an element size being one of 1 byte, 2 bytes, 4 bytes, 8 bytes, and 16 bytes;
decoding, using decode circuitry, the fetched matrix transpose instruction;
and
executing, using execution circuitry, responsive to the decoded matrix transpose instruction to, for each row X of M rows of the source matrix:
fetch and buffer N elements of the row in a load register;
and
cause the N buffered elements to be written, in the same relative order as in the row, to column X of M columns of a load buffer, the load buffer being distinct from the load register and having (N×M) elements;
and
the execution circuitry subsequently to write each of N rows of the load buffer to a same row of the destination matrix.

6 more elements

Dependencies are inferred from the claim text.

Method and apparatus for efficient matrix transpose

Life of this patent

Method and apparatus for efficient matrix transpose

Life of this patent

Abstract

Claims18