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US 10,649,771 B2Granted
Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsHyun Pil Kim, Hyun Woo Sim, Seong Woo Ahn
Life of this patent
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Abstract
A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.
Claims14
A semiconductor device, comprising:
- a first processor comprising a first register, the first processor configured to perform region of interest (ROI) calculations using the first register and to process instructions according to a single instruction multiple data (SIMD) architecture;
- and
- a second processor comprising a second register, the second processor configured to perform arithmetic calculations using the second register and to process instructions according to a very long instruction word (VLIW) architecture,
- wherein the first register is shared with the second processor, and the second register is shared with the first processor,
- wherein the instructions processed by the second processor comprise two or more slots, and
- wherein at least one slot of the two or more slots is executed using the first processor.
3 more elements
A semiconductor device, comprising:
- a first processor comprising a first register, the first processor configured to perform region of interest (ROI) calculations using the first register and to process instructions according to a single instruction multiple data (SIMD) architecture;
- and
- a second processor comprising a second register, the second processor configured to perform arithmetic calculations using the second register and to process instructions according to a very long instruction word (VLIW) architecture,
- wherein the first processor and the second processor share a same instruction set architecture (ISA), and
- wherein the instructions processed by the second processor are processed at two or more slots, and at least one of the two or more slots is executed using the first processor.
2 more elements
Dependencies are inferred from the claim text.