Instruction and logic to perform dynamic binary translation

A processor comprising:

• a die;
• execution units on the die to execute instructions of software code compiled targeting a first instruction set;
• a performance measure unit to detect a hot spot in the software code, wherein the processor is to pass control to a binary translation translator upon the detection of the hot spot;
• and
• said execution units also to execute translated code corresponding to the hot spot, which is to have been generated by the binary translation translator, from a translation cache, wherein the translated code is to include instructions that are not included in the first instruction set that are part of an instruction set extension to the first instruction set;
• and
• hardware to temporarily store results associated with the execution of the translated code, and to either atomically discard the results or atomically commit the results,
• wherein the execution units are to execute the translated code on vector registers even when an operating system and a virtual machine monitor do not support saving and restoring state to the vector registers.

A processor comprising:

• a die;
• execution units on the die to execute instructions of software code compiled targeting a first instruction set;
• a performance measure unit to detect a hot spot in the software code, wherein the processor is to pass control to a binary translation translator upon the detection of the hot spot;
• said execution units also to execute translated code corresponding to the hot spot, which is to have been generated by the binary translation translator, from a translation cache, wherein the execution units are to execute the translated code with wider vectors than all vectors that are to be used by the software code, even when one or more of an operating system and a virtual machine monitor do not support saving and restoring state to registers having a same width as the wider vectors,
• wherein the processor is to temporarily store results associated with the execution of the translated code and is to discard the results upon occurrence of at least one of an interrupt and an exception before execution of all of the translated code has finished.

A computer system comprising:

• a storage, having at least one memory device, to store software code compiled targeting a first instruction set;
• and
• a processor, having at least one hardware processor core, coupled with the storage, the processor to:
• execute the software code;
• detect, with a performance measure unit of the processor, a hot spot in the software code;
• pass control to a binary translation translator after the detection of the hot spot;
• execute translated code that is to correspond to the hot spot from a translation cache, wherein the translated code is to include instructions that are not included in the first instruction set that are part of an instruction set Single Instruction Multiple Data (SIMD) extension to the first instruction set, and wherein the translated code is to use wider vectors than all those to be used by the software code;
• temporarily store results associated with the execution of the translated code;
• atomically discard the results upon occurrence of at least one of an interrupt and an exception before execution of all of the translated code has finished;
• or
• atomically commit the results if said at least one of the interrupt and the exception does not occur before the execution of said all of the translated code has finished.