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US 10,649,737 B2Granted
Reverse conversion apparatus for residue numbers
AssigneeOlsen IP Reserve, LLC
InventorEric B. Olsen
Life of this patent
Estimating the term…
Abstract
Arithmetic circuits and methods that perform efficient conversion of fractional RNS representations to fractional binary representations is disclosed herein.
Claims5
A reverse conversion hardware pipeline for conversion of a signed fixed-point residue number having a fractional portion and a whole number portion to a signed fixed-point binary number comprising:
- a first register that receives a scaled RNS value generated based on the signed fixed-point residue number;
- a mixed-radix converter coupled to the first register and comprising one or more stages, wherein:
- for each of the one or more stages, the mixed-radix converter generates one or more mixed radix digits, one or more rounding bits, and a sign bit associated with a whole range of the scaled RNS value;
- and
- at a last of the one or more stages, the mixed-radix converter stores a signed mixed-radix integer;
- a binary converter coupled to the mixed-radix converter and comprising one or more pipeline stages, wherein:
- for each of the one or more pipeline stages, the binary converter shifts said signed mixed-radix integer;
- and
- at a last of the one or more pipeline stages, the binary converter stores a binary number;
- and
- a second register that receives the binary number or a corrected binary number when the binary number is negative, wherein the corrected binary number is generated by arithmetically applying a correction constant to the binary number;
- wherein the second register stores the signed fixed-point binary number.
9 more elements
A reverse conversion hardware pipeline for conversion of a signed fixed-point residue number having a fractional portion and a whole number portion to a signed fixed-point binary number comprising:
- a first register that receives a scaled RNS value generated based on the signed fixed-point residue number;
- a mixed-radix converter coupled to the first register and comprising one or more second registers, wherein:
- for each of the one or more second registers, the mixed-radix converter generates one or more mixed radix digits, one or more rounding bits, and a sign bit associated with a whole range of the scaled RNS value;
- and
- at at least one of the one or more second registers, the mixed-radix converter stores a signed mixed-radix integer;
- a binary converter coupled to the mixed-radix converter and comprising one or more pipeline registers, wherein:
- for each of the one or more pipeline registers, the binary converter shifts the signed mixed-radix integer;
- and
- at at least one of the one or more pipeline stages, the binary converter stores a binary number;
- and
- a third register that receives the binary number or a corrected binary number when the binary number is negative, wherein the corrected binary number is generated by arithmetically applying a correction constant to the binary number;
- wherein the third register stores the signed fixed-point binary number.
9 more elements
Dependencies are inferred from the claim text.