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US 10,649,736 B2Granted
Normalization unit for signed operands
AssigneeOlsen IP Reserve, LLC
InventorEric B. Olsen
Life of this patent
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Abstract
Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.
Claims6
A method for normalizing signed numbers comprising a plurality of residue digits having a whole range and a fractional range with a pipelined processor, the pipelined processor having at least one pipeline, the method comprising:
- receiving a non-normalized intermediate product at an input of the pipelined processor;
- converting the non-normalized intermediate product to a plurality of mixed-radix digits associated with a fractional range, producing one or more remaining residue digits associated with the whole range;
- storing the one or more remaining residue digits associated with the whole range in one or more pipelined registers, and producing a partial result comprising one or more whole digits;
- delaying the partial result to exit the at least one pipeline;
- reconverting one or more of the plurality of mixed radix digits associated with the fractional range to generate an uncorrected fractional result in a residue format;
- when the partial result is a negative value, generating one or more corrected fractional digits by summing a correction constant with the uncorrected fractional result;
- and
- concatenating the partial result and the one or more corrected fractional digits to generate a signed normalized product;
- wherein the partial result and the one or more corrected fractional digits exit the at least one pipeline as the signed normalized product.
6 more elements
Dependencies are inferred from the claim text.