Processing circuitry

A processing circuit comprising:

• a first time-encoding modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first pulse-width-modulation (PWM) signal with a cycle frequency that depends substantially on the square of the value of the first combined signal;
• a second time-encoding modulator configured to receive a second combined signal corresponding to a difference between said first input signal and said second input signal and to generate a second PWM signal with a cycle frequency that depends substantially on the square of the value of the second combined signal;
• a first time-decoding converter configured to receive the first PWM signal and to provide a first count value based on a first parameter of the first PWM signal;
• a second time-decoding converter configured to receive the second PWM signal and to provide a second count value based on a second parameter of the second PWM signal;
• and
• a subtractor configured to determine a difference between the first and second count values and to output an output signal based on said difference between the first and second count values;
• wherein the first time-decoding converter and the second time-decoding converter each comprise a counter configured to receive a reference clock signal and to count a number of cycles of the reference clock signal in a PWM cycle period defined by the respective one of the first or second PWM signals to provide the respective first or second count value.

A processing circuit comprising:

• a first time-encoding modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first pulse-width-modulation (PWM) signal with a cycle frequency that depends substantially on the square of the value of the first combined signal;
• a second time-encoding modulator configured to receive a second combined signal corresponding to a difference between said first input signal and said second input signal and to generate a second PWM signal with a cycle frequency that depends substantially on the square of the value of the second combined signal;
• a first time-decoding converter configured to receive the first PWM signal and to provide a first count value based on a first parameter of the first PWM signal;
• a second time-decoding converter configured to receive the second PWM signal and to provide a second count value based on a second parameter of the second PWM signal;
• and
• a subtractor configured to determine a difference between the first and second count values and to output an output signal based on said difference between the first and second count values;
• wherein each of the first time-encoding modulator and the second time-encoding modulator comprises:
• a forward signal path configured to receive the respective first or second combined signal at a first input;
• a feedback path forming a feedback loop with at least part of the forward signal path;
• a comparator located in the forward signal path within the feedback loop;
• and
• a filter arrangement within the feedback loop.

A multiplication circuit for multiplying a first input value by a second input value comprising:

• a first signal path configured to receive a first signal with a value corresponding to the sum of the first input value and the second input value and to generate a first output value which is a function of the square of the value of the first signal;
• a second signal path configured to receive a second signal with a value corresponding to the difference between the first input value and the second input value and to generate a second output value which is a function of the square of the value of the second signal;
• and
• a subtractor for determining a difference between the first output value and the second output value;
• wherein each of the first and second signal paths comprises a self-oscillating time-encoding modulator and a time-decoding converter;
• and
• wherein the time-decoding converter in each of the first and second signal paths comprises a respective counter configured to receive a reference clock signal and wherein the multiplication circuit is selectively operable in a first mode or a second mode, wherein:
• in the first mode of operation the counter of the time-decoding converter is configured count a number of cycles in an output of the respective self-oscillating time-encoding modulator in each of a succession of count periods defined by the reference clock signal to provide a count value;
• in the second mode of operation the counter of the time-decoding converter is configured to count a number of cycles of the reference clock signal in a cycle period defined by the output of the respective self-oscillating time-encoding modulator to provide the count value;
• and
• the frequency of the reference clock signal is greater in the second mode than in the first mode.

A processing circuit comprising:

• a signal combiner configured to receive first and second input signals and to generate a first combined signal corresponding to a sum of the first and second input signals and a second combined signal corresponding to a difference between the first and second input signals;
• first and second time-encoding modulators configured to receive the first and second combined signals respectively and generate respective first and second cyclic signals each with a respective cycle frequency, wherein the respective cycle frequency is substantially proportional to (1−R2) where R is a value of the respective input to the respective time-encoding modulator normalised within a range of −1 to +1 with respect to an input range of the respective time-encoding modulator;
• and
• first and second counters configured to receive the first and second cyclic signals respectively and produce first and second count values;
• and
• a subtractor configured to determine a difference between the first and second count values;
• wherein the first and second counters are each configured to generate a count value of a number of cycles of the first or the second cyclic signal in a count period defined by a reference clock signal.