Memory buffer management and bypass
AssigneeMicron Technology, Inc.
InventorsRobert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.
Claims20
An apparatus, comprising:
- a memory array configured according to a first memory page size;
- a virtual memory bank coupled with the memory array;
- a buffer coupled with the virtual memory bank;
- and
- a controller coupled with the memory array and the virtual memory bank, the controller to interface with a host, the controller comprising:
- a memory interface component to receive data corresponding to the first memory page size of the memory array;
- a counter management component to increment a value of a counter associated with the virtual memory bank based at least in part on a memory access operation associated with the data;
- and
- a data management component to communicate the data between the virtual memory bank and the buffer based at least in part on the value of the counter satisfying a threshold.
An apparatus, comprising:
- a memory subsystem comprising:
- a memory array to store first data having a first page size;
- a virtual memory bank coupled with the memory array and to receive the first data during a memory access operation, the virtual memory bank comprising a saturation counter to increment a count based at least in part on the virtual memory bank receiving the first data;
- and
- a controller coupled with the virtual memory bank and to transfer the first data from the virtual memory bank to a buffer based at least in part on the count of the saturation counter satisfying a threshold value.
An apparatus, comprising:
- a memory array having a page size and comprising memory cells;
- a virtual memory bank coupled with the memory array;
- a buffer;
- and
- a controller coupled with the virtual memory bank and the buffer, the controller to interface with a system on a chip (SoC) or processor, the controller operable to:
- receive data corresponding to a page of the memory array;
- determine whether to communicate the data to the buffer or the memory array based at least in part on a characteristic of the data;
- and
- communicate the data between the virtual memory bank and the buffer or the memory array based at least in part on the characteristic of the data.
Dependencies are inferred from the claim text.