US 10,649,487 B2Granted

Fail-safe clock monitor with fault injection

AssigneeMicrochip Technology Incorporated

InventorsKevin Kilzer, Aditya Nukala

Life of this patent

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Abstract

A system for testing a clock monitor includes a fault injection circuit, a control circuit, and a clock monitor circuit to evaluate a clock source signal from a clock source. The fault injection circuit is to modify or replace the clock source signal from the clock source to yield a modified clock signal, and send the modified clock signal to the clock monitor circuit. The clock monitor circuit is to receive an input clock signal, determine whether the input clock signal indicates a faulty clock source, and issue a clock corrective action if the input clock signal indicates a faulty clock source. The control circuit is to monitor for the clock corrective action, and determine, based on whether the clock corrective action is issued, whether the clock monitor circuit is operating correctly.

Claims20

Dependent claims

A system for testing a clock monitor, comprising:

a fault injection circuit with an input communicatively coupled to a clock source;
a control circuit;
and
a clock monitor circuit communicatively coupled to an output of the fault injection circuit and to an input of the control circuit, the clock monitor circuit configured to evaluate a clock source signal from the clock source;
wherein:
the fault injection circuit is configured to:
modify or replace the clock source signal from the clock source to yield a modified clock signal;
and
send the modified clock signal to the clock monitor circuit;
the clock monitor circuit is configured to:
receive an input clock signal;
determine whether the input clock signal indicates a faulty clock source;
and
issue a clock corrective action based upon a determination that the input clock signal indicates a faulty clock source;
and
the control circuit is configured to:
monitor for the clock corrective action;
and
determine based on whether the clock corrective action is issued whether the clock monitor circuit is operating correctly.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/143,841Filed 27 Sep 2018 · us provisional application
Priority: 5 Jul 2018
Published: US 2020/0012313 A19 Jan 2020
Granted: 12 May 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G01R 31/31727
Testing of digital circuits: clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing…
G06F 1/14
Generating or distributing clock signals or signals derived directly therefrom: time supervision arrangements, e.g. real time clock
G06F 1/04
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: generating or distributing clock signals or signals derived directly therefrom
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency