Array substrate, display panel and display device

An array substrate, comprising a plurality of signal lines, wherein each signal line is connected to a plurality of subpixel units, the plurality of signal lines comprises first signal lines;

• the plurality of subpixel units connected to each first signal line is divided into at least two groups of subpixel units, each group of subpixel units comprises at least one subpixel unit;
• an overlapping area between a common electrode and a pixel electrode of each subpixel unit in a group of subpixel units adjacent to a signal input end of the first signal line is larger than an overlapping area between a common electrode and a pixel electrode of each subpixel unit in a group of subpixel units away from the signal input end of the first signal line;
• each subpixel unit in the at least two groups of subpixel units corresponding to each first signal line comprises a transparent pixel electrode and a transparent common electrode arranged at a layer different from the transparent pixel electrode, the pixel electrodes of the subpixel units in the at least two groups of subpixel units have a same size, and sizes of the common electrodes of the subpixel units in the at least two groups of subpixel units gradually decrease in a direction away from the signal input end of the first signal line;
• the at least two groups of subpixel units corresponding to each first signal line comprises a first group of subpixel units arranged adjacent to the signal input end of the first signal line and a second group of subpixel units arranged away from the signal input end of the first signal line, the common electrode of the subpixel unit in the first group of subpixel units is of a plate-like shape, and the pixel electrode of each subpixel unit in the second group of subpixel units is of a comb-like shape.

An array substrate, comprising a plurality of signal lines each connected to a plurality of subpixel units, wherein

• the plurality of signal lines comprises first signal lines;
• the plurality of subpixel units connected to each first signal line is divided into at least two groups of subpixel units, each group of subpixel units includes at least one subpixel unit;
• and
• a capacitance of a storage capacitor formed between a common electrode and a pixel electrode of each subpixel unit in a group of subpixel units adjacent to a signal input end of the first signal line is larger than a capacitance of a storage capacitor formed between a common electrode and a pixel electrode of each subpixel unit in a group of subpixel units away from the signal input end of the first signal line,
• wherein the at least two groups of subpixel units corresponding to each first signal line comprise a first group of subpixel units arranged adjacent to the signal input end of the first signal line and a second group of subpixel units arranged away from the signal input end of the first signal line;
• each subpixel unit in the first group of subpixel units comprises a transparent pixel electrode and a transparent common electrode arranged at a layer different from the pixel electrode, and a first storage capacitor is formed between the pixel electrode and the common electrode of the subpixel unit in the first group of subpixel units;
• each subpixel unit in the second group of subpixel units comprises a transparent pixel electrode, a transparent common electrode arranged at a layer same as the pixel electrode and a nontransparent common electrode line arranged at a layer different from the pixel electrode, a second storage capacitor is formed between the pixel electrode and the common electrode line of the subpixel unit in the second group of subpixel units;
• and
• the first storage capacitor has a capacitance greater than that of the second storage capacitor.