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US 10,649,032 B2Granted
Core circuitry, tap domain circuitry, separate auxiliary circuitry, output buffers
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.
Claims4
An integrated circuit comprising:
- (a) core circuitry;
- (b) tap domain circuitry coupled to the core circuitry, the tap domain circuitry including a test data input, a test data output, a test clock input, a test mode select input, and control outputs;
- (c) auxiliary circuitry separate from the tap domain circuitry, the auxiliary circuitry having auxiliary inputs, auxiliary outputs, a control input coupled to the control outputs, and output buffer control outputs;
- and
- (d) output buffers, each output buffer having an input coupled to an auxiliary output, a control input coupled to an output buffer control output, and an output;
- (e) the tap domain circuitry including:
- controller circuitry having a clock input coupled to the test clock input, a mode select input coupled to the test mode select input, and the control outputs;
- instruction register circuitry having a data input coupled to the test data input, an instruction data output, an instruction control output, and a control input coupled to the control outputs;
- data register circuitry having a data input coupled to the test data input, a data register data output, an instruction control input coupled to the instruction control output, and a control input coupled to the control outputs;
- multiplexer circuitry having an instruction data input coupled to the instruction data output, a data register data input coupled to the data register data output, a control input coupled to the control outputs, and a multiplexer output;
- and
- test data out register having an input coupled to the multiplexer output, a control input coupled to the control outputs, and a data output coupled to the test data output.
9 more elements
An integrated circuit comprising:
- (a) core circuitry;
- (b) tap domain circuitry coupled to the core circuitry, the tap domain circuitry including a test data input, a test data output, a test clock input, a test mode select input, and control outputs;
- (c) auxiliary circuitry separate from the tap domain circuitry, the auxiliary circuitry having auxiliary inputs, auxiliary outputs, a control input coupled to the control outputs, and output buffer control outputs;
- and
- (d) output buffers, each output buffer having an input coupled to an auxiliary output, a control input coupled to an output buffer control output, and an output;
- (e) in which the auxiliary circuitry includes digital circuitry.
3 more elements
An integrated circuit comprising:
- (a) core circuitry;
- (b) tap domain circuitry coupled to the core circuitry, the tap domain circuitry including a test data input, a test data output, a test clock input, a test mode select input, and control outputs;
- (c) auxiliary circuitry separate from the tap domain circuitry, the auxiliary circuitry having auxiliary inputs, auxiliary outputs, a control input coupled to the control outputs, and output buffer control outputs;
- and
- (d) output buffers, each output buffer having an input coupled to an auxiliary output, a control input coupled to an output buffer control output, and an output;
- (e) including input buffers, each input buffer having an input coupled to the output of an output buffer and an output coupled to an auxiliary input.
3 more elements
Dependencies are inferred from the claim text.