Hardware assisted high speed serial transceiver testing

An integrated circuit for hardware assisted high speed serial (HSS) transceiver testing, wherein the integrated circuit comprises a hardware state machine, and wherein the integrated circuit is configured to carry out the steps of:

• receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units, wherein the HSS transmitting device comprises the link layer hardware state machine, a HSS transceiver, and embedded random access memory (RAM);
• loading, by the link layer hardware state machine, each unique data unit of the test pattern into the embedded RAM;
• generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern;
• and
• sending, by the link layer hardware state machine of the HSS transmitting device, the generated test pattern to an input of the HSS transceiver of the HSS transmitting device, wherein an output of the HSS transceiver is tested by comparing the output test pattern of the HSS transceiver to an expected output test pattern.

A computer program product for hardware assisted high speed serial (HSS) transceiver testing, the computer program product disposed upon a computer readable storage medium, the computer program product comprising computer program instructions that, when executed, cause an integrated circuit to carry out the steps of:

• receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units, wherein the HSS transmitting device comprises the link layer hardware state machine, a HSS transceiver, and embedded random access memory (RAM);
• loading, by the link layer hardware state machine, each unique data unit of the test pattern into the embedded RAM;
• generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern;
• and
• sending, by the link layer hardware state machine of the HSS transmitting device, the generated test pattern to an input of the HSS transceiver of the HSS transmitting device, wherein an output of the HSS transceiver is tested by comparing the output test pattern of the HSS transceiver to an expected output test pattern.