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US 10,649,029 B2Granted
TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs
AssigneeTexas Instruments Incorporated
InventorGary L. Swoboda
Life of this patent
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Abstract
Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.
Claims9
An integrated circuit comprising:
- (a) a test clock line;
- (b) a test mode select counter line;
- (c) first circuitry having inputs coupled to the test clock line and to the test mode select counter line, and having a count clock output line, the first circuitry including a flip flop having a clock input coupled to the test clock line, a data input coupled to the test mode select counter line, and a non-inverting output coupled to the count clock output line;
- (d) counter circuitry having a count clock input connected to the count clock output line, the counter circuitry having stages, a first stage having a first count output, a second stage having a second count output, a third stage having a third count output, and a fourth stage having a fourth count output, the counter circuitry having a reset output coupled to the fourth count output;
- (e) first gating circuitry having inputs connected to the second and third count outputs, having a deselection output line, and having a selection output line;
- and
- (f) second gating circuitry having inputs connected to the first and second count outputs and having a technology specific function output line.
4 more elements
Dependencies are inferred from the claim text.