Logic built in self test circuitry for use in an integrated circuit with scan chains

A system comprising logic built-in self-test (LBIST) circuitry for use in an integrated circuit with scan chains, the system comprising:

• a pattern generator configured for generating scan-in test values for said scan chains;
• a signature register configured for collecting scan-out responses from said scan chains after a clock sequence;
• an on product control generator configured to control at least one test parameter applied to said scan chains;
• a microcode array configured to receive multiple sets of test parameters to initialize the microcode array with a setup for a plurality of LBIST patterns, wherein initializing the microcode includes initializing fields of the microcode array with the multiple sets of test parameters, wherein each set of test parameters of the multiple sets of test parameters is associated with a different LBIST pattern of the plurality of LBIST patterns, and wherein the microcode array is initialized only once before the plurality of LBIST patterns are executed;
• and
• a test controller comprising:
• a reader component configured for reading test parameters associated with a first LIBIST pattern of the plurality of LBIST patterns from a field of the microcode array;
• a programming component configured for configuring the on product control generator and the pattern generator with the first LBIST pattern, wherein the first LBIST pattern comprises at least a number of loops, wherein the test controller is configured to repeatedly read test parameters associated with other LIBST patterns of the plurality of LBIST patterns from fields of said microcode array via the reader component and to configure the on-product control generator and the pattern generator with the other LBIST patterns according to the read test parameters randomly;
• and
• a communication component configured for communicating with a chip tester, the communication component comprising:
• a receiving component configured for receiving a start request from the chip tester;
• a starting component configured for triggering the test controller responsive to said receiving component;
• and
• a reporting component configured for, responsive to said test controller, communicating test summary data to said chip tester before the whole number of loops have been executed.