Back to results
US 10,644,714 B2Granted
Pipelined analog-to-digital converter
AssigneeTexas Instruments Incorporated
InventorsArun Mohan, Neeraj Shrivastava
Life of this patent
Estimating the term…
Abstract
An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.
Claims18
An analog-to-digital converter (ADC), comprising:
- a first stage including:
- a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output;
- a buffer having an input coupled to the first SH output, and having a buffer output;
- a first flash converter having an input coupled to the first SH output, and having a first flash converter output;
- and
- a first digital-to-analog converter (DAC) having an input coupled to the first flash converter output;
- and
- a second stage including a second flash converter having an input coupled to the buffer output;
- wherein the second flash converter is configured to be clocked based on a control signal derived from the first flash converter.
6 more elements
An analog-to-digital converter (ADC), comprising:
- a first stage including:
- a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output;
- a buffer having an input coupled to the first SH output, and having a buffer output;
- a first flash converter having an input coupled to the first SH output, and having a first flash converter output;
- and
- a first digital-to-analog converter (DAC) having an input coupled to the first flash converter output;
- and
- a second stage including a second flash converter having an input coupled to the buffer output;
- wherein the first flash converter includes a plurality of comparators, each of the plurality of comparators having a comparator output, and the ADC further comprises a first logic circuit coupled to the comparator output of each of the plurality of comparators.
6 more elements
An analog-to-digital converter (ADC), comprising:
- a first stage including:
- a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output;
- a buffer having an input coupled to the first SH output, and having a buffer output;
- a first flash converter having an input coupled to the first SH output, and having a first flash converter output;
- and
- a first digital-to-analog converter (DAC) having an input coupled to the first flash converter output;
- and
- a second stage including a second flash converter having an input coupled to the buffer output;
- wherein the second flash converter comprises a plurality of comparators, and each of the plurality of comparators includes a pre-amplifier and a latch, wherein the latch is configured to be clocked asynchronously with respect to the pre-amplifier.
6 more elements
A transceiver, comprising:
- a transmitter;
- and
- an analog-to-digital converter (ADC) coupled to the transmitter, the ADC comprising a first stage and a second stage;
- the first stage including:
- a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output;
- a buffer having an input coupled to the first SH output, and having a buffer output;
- a first flash converter having an input coupled to the first SH output, and having a first flash converter output;
- and
- a first digital-to-analog converter (DAC) having an input coupled to the first flash converter output;
- and
- the second stage including a second flash converter having an input coupled to the buffer output;
- wherein the second flash converter is configured to be clocked based on a control signal derived from the first flash converter.
9 more elements
A transceiver, comprising:
- a transmitter;
- and
- an analog-to-digital converter (ADC) coupled to the transmitter, the ADC comprising a first stage and a second stage;
- the first stage including:
- a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output;
- a buffer having an input coupled to the first SH output, and having a buffer output;
- a first flash converter having an input coupled to the first SH output, and having a first flash converter output;
- and
- a first digital-to-analog converter (DAC) having an input coupled to the first flash converter output;
- and
- the second stage including a second flash converter having an input coupled to the buffer output;
- wherein the first flash converter includes a plurality of comparators, each of the plurality of comparators having a comparator output, and the ADC further comprises a first logic circuit coupled to the comparator output of each of the plurality of comparators, and wherein the first logic circuit is configured to generate a logic 1 responsive to one of the comparator outputs being a logic 1 and another comparator output is a logic 0.
9 more elements
A transceiver, comprising:
- a transmitter;
- and
- an analog-to-digital converter (ADC) coupled to the transmitter, the ADC comprising a first stage and a second stage;
- the first stage including:
- a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output;
- a buffer having an input coupled to the first SH output, and having a buffer output;
- a first flash converter having an input coupled to the first SH output, and having a first flash converter output;
- and
- a first digital-to-analog converter (DAC) having an input coupled to the first flash converter output;
- and
- the second stage including a second flash converter having an input coupled to the buffer output;
- wherein the first flash converter includes a plurality of comparators, each of the plurality of comparators having a comparator output, and the ADC further comprises a first logic circuit coupled to the comparator output of each of the plurality of comparators, and wherein the second flash converter includes a plurality of comparators, and the ADC further includes a multiplexer coupled to the second flash converter's plurality of comparators, the multiplexer being configured to select, as an output from the multiplexer, a subset of the second flash converter's plurality of comparators.
9 more elements
A transceiver, comprising:
- a transmitter;
- and
- an analog-to-digital converter (ADC) coupled to the transmitter, the ADC comprising a first stage and a second stage;
- the first stage including:
- a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output;
- a buffer having an input coupled to the first SH output, and having a buffer output;
- a first flash converter having an input coupled to the first SH output, and having a first flash converter output;
- and
- a first digital-to-analog converter (DAC) having an input coupled to the first flash converter output;
- and
- the second stage including a second flash converter having an input coupled to the buffer output;
- wherein the second flash converter comprises a plurality of comparators, and each of the plurality of comparators includes a pre-amplifier and a latch, wherein the latch is configured to be clocked asynchronously with respect to the pre-amplifier.
9 more elements
An analog-to-digital converter (ADC), comprising:
- a first stage including:
- a buffer having an input configured to receive a sampled input voltage, and having a buffer output;
- a first flash converter having an input configured to receive the sampled input voltage, and having a first flash converter output;
- and
- a first digital-to-analog converter (DAC) having an input coupled to the first flash converter output;
- and
- a second stage including a second flash converter having an input coupled to the buffer output, the second flash converter configured to operate using a control signal derived from the first flash converter.
4 more elements
Dependencies are inferred from the claim text.