US 10,643,695 B1 · Concurrent multi-state program verify for non-volatile memory

Abstract

A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. By allowing the sense amplifier to bias a memory cell being sensed to a selected one of multiple bias levels during a sensing operation, multiple target data states can be concurrently program verified, leading to higher performance when writing data.

Claims19

Dependent claims

An apparatus, comprising:

a word line;
a source line;
a plurality of memory cells connected along the word line;
a plurality of bit lines;
and
a plurality of sense amplifier circuits each coupled to a corresponding one of the memory cells though one of the bit lines, the sense amplifier circuits configured to concurrently:
bias bit lines connected to a first set of the memory cells to a first voltage level;
bias bit lines connected to a second set of the memory cells to a second voltage level;
and
discharge a source line voltage from the source line through each memory cell of the first set and second set to the corresponding sense amplifier circuit in response to a first, non-negative sensing voltage level applied to the word line.

7 more elements

A sense amplifier circuit, comprising:

a first bias path configured to bias a selected memory cell connected to the sense amplifier circuit to a first voltage level;
a second bias path configured to bias the selected memory cell to a second voltage level;
switching circuits configured to sense the selected memory cell by selectively biasing the selected memory cell to one of the first voltage level and the second voltage level and, while the selected memory cell is selectively biased to one of the first voltage level and the second voltage level, discharging a current through the selected memory cell;
and
a third bias path configured to bias the selected memory cell to a program inhibit voltage, wherein the switching circuits are further configured to selectively bias the selected memory cell to the program inhibit voltage.

2 more elements

A method, comprising:

applying a programming pulse to a word line connected to a plurality of memory cells;
and
subsequently performing a verify, comprising:
biasing the word line to a first sensing voltage;
and
while biasing the word line to the first sensing voltage, concurrently sensing a first set of a selected one or more of the memory cells for a first data state and a second set of a selected one or more of the memory cells for a second data state, including:
for each of the memory cells of the first set, biasing a corresponding bit line to a first bit line voltage and measuring an amount of current through the memory cell from a source line to the corresponding bit line;
and
for each of the memory cells of the second set, biasing a corresponding bit line to a second bit line voltage and measuring an amount of current through the memory cell from the source line to the corresponding bit line.

6 more elements

Dependencies are inferred from the claim text.

Concurrent multi-state program verify for non-volatile memory

Life of this patent

Concurrent multi-state program verify for non-volatile memory

Life of this patent

Abstract

Claims19