Binary, ternary and bit serial compute-in-memory circuits

An apparatus, comprising:

• a compute-in-memory (CIM) circuit, the CIM circuit comprising a computation circuit coupled to a memory array of memory cells for storing a binary weight matrix, the computation circuit comprising:
• precharged bitlines of equal capacitance coupled to columns of memory cells of the memory array;
• wordlines coupled to rows of memory cells of the memory array;
• column switch capacitors coupled to the precharged bitlines of equal capacitance;
• wherein the computation circuit to:
• generate pulses of fixed duration across the rows of memory cells based on an input vector to the computation circuit,
• capture on the precharged bitlines an amount of voltage drop for memory cells that discharge to the precharged bitlines in response to the pulses of fixed duration, the amount of voltage drop for a bitcell equivalent to an amount of voltage drop for any other bitcell that discharges to the precharged bitlines, and
• accumulate, in the column switch capacitors, equivalent amounts of voltage drop on the precharged bitlines of equal capacitance;
• and
• wherein an accumulated voltage drop on all the precharged bitlines represents a binary dot product of the input vector and the binary weight matrix.

A system comprising:

• a processor;
• a memory device communicatively coupled with the processor, the memory device including a compute-in-memory (CIM) circuit, the CIM circuit comprising a computation circuit coupled to a memory array, the computation circuit comprising:
• a memory array of memory cells to store a binary weight matrix;
• a memory access circuit of bitlines having equal capacitance and wordlines driven with pulses of fixed duration based on an input vector, the pulses to activate one or more memory cells in the memory array;
• the memory access circuit to enable an activated bitcell in the memory array to cause a voltage drop in a bitline to which the activated bitcell is coupled, wherein the voltage drop is equivalent to voltage drops caused by other activated memory cells in the memory array;
• and
• a capacitor circuit coupled to the bitlines to accumulate bitline voltages after voltage drops into a voltage output, the voltage output to represent a binary dot product of the input vector and the binary weight matrix stored in the memory array.