US 10,623,174 B1Granted

Low latency data transfer technique for mesochronous divided clocks

AssigneeXilinx, Inc.

InventorsRiyas Noorudeen Remla, Warren E. Cory, Chee Chong Chan

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Abstract

Electrical circuits and associated methods relate to performing a phase alignment by providing N copies of clock alignment circuits, enabling and selecting different clock alignment circuits to achieve an initial phase alignment. In an illustrative example, a phase alignment circuit may include a first clock alignment circuit configured to find a first phase alignment point and a second clock alignment circuit configured to find a second phase alignment point. A control circuit may be configured to select a primary clock alignment circuit from the first clock alignment circuit and the second clock alignment circuit and generate a digital command signal to control a phase interpolator. In various embodiments, by setting the control circuit, the same phase alignment circuit may be used to perform phase alignments between clock domains with different frequencies.

Claims20

Dependent claims

A system comprising:

a first clock alignment circuit configured to monitor a received beacon signal and generate a first command signal in response to a first detected phase alignment point between an incoming beacon signal and a first clock signal, wherein the received beacon signal is generated by a synchronizer in response to the incoming beacon signal and the first clock signal;
a second clock alignment circuit configured to monitor the received beacon signal and generate a second command signal in response to a second detected phase alignment point between the incoming beacon signal and the first clock signal;
and,
a control circuit configured to, in response to a faster one of the first detected phase alignment point and the second detected phase alignment point, select a primary clock alignment circuit from the first clock alignment circuit and the second clock alignment circuit to output a corresponding command signal of the selected primary clock alignment circuit to control a phase interpolator,
wherein, the first clock signal is output by the phase interpolator configured to adjust a phase of a receiving clock signal in response to the selected command signal, the control circuit is further configured to generate a toggling enable signal to enable the first clock alignment circuit and the second clock alignment circuit alternately.

2 more elements

A phase alignment method, comprising:

providing a first clock alignment circuit to monitor a received beacon signal and generate a first command signal in response to a first detected phase alignment point between an incoming beacon signal and a first clock signal, wherein the received beacon signal is generated by a synchronizer in response to the incoming beacon signal and the first clock signal;
providing a second clock alignment circuit to monitor the received beacon signal and generate a second command signal in response to a second detected phase alignment point between the incoming beacon signal and the first clock signal;
generating, with a control circuit, an enable signal to enable the first clock alignment circuit and the second clock alignment circuit;
and,
selecting, by the control circuit, a primary clock alignment circuit from the first and the second clock alignment circuits to output a corresponding a command signal of the selected primary clock alignment circuit to control a phase interpolator,
wherein, the selected primary clock alignment circuit is the one that detects a phase alignment point first, and the first clock signal is output by the phase interpolator configured to adjust a phase of a receiving clock signal in response to the selected command signal.

3 more elements

Dependencies are inferred from the claim text.