Precision digital to analog conversion in the presence of variable and uncertain fractional bit contributions

A match network comprising one or more variable capacitors, each of the one or more variable capacitors comprising:

• a digital input;
• N switched capacitors each having an on and an off state that is controlled by the digital input and an output;
• an interconnect network coupled to each of the N switched capacitors, wherein the interconnect network is configured to provide a sum of the contributions of the N switched capacitors to a capacitance of the variable capacitor between terminals of the output;
• wherein for each one of the N switched capacitors:
• a contribution of one of the N switched capacitors is a change in the variable capacitor capacitance when a state of the one of the switched capacitors is switched from off to on and all remaining N−1 switched capacitors' states remain the same, and
• the contribution of at least one of the switched capacitors varies across a range based on the states of the remaining N−1 switched capacitors;
• wherein the N switched capacitors are ordered from smallest to largest via an average of each switched capacitors' range of contributions to the variable capacitor capacitance,
• wherein a gap size, D, is less than or equal to two times a maximum of a contribution of a first of the N switched capacitors, and
• for k ranging from two to N, a maximum contribution of a kth switched capacitor is less than or equal to D plus a sum of minimum contributions of switched capacitor 1 through switched capacitor k−1.

A method of forming a variable capacitor, the method comprising:

• providing a digital input;
• providing N switched capacitors coupled to each other via an interconnect topology;
• providing an analog output, from the interconnect topology as a sum of capacitance contributions of the N switched capacitors;
• and
• selecting the N capacitors to form a sub-binary sequence, where a maximum contribution of a kth switched capacitor is less than or equal to a gap size, D, plus a sum of minimum contributions of a first to a (k−1)th switched capacitor.